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wdenk56f94be2002-11-05 16:35:14 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenk56f94be2002-11-05 16:35:14 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk65faef92004-03-25 19:29:38 +000016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk56f94be2002-11-05 16:35:14 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 * Derived from ../tqm8xx/tqm8xx.c
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
39#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
40
wdenk65faef92004-03-25 19:29:38 +000041#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenk56f94be2002-11-05 16:35:14 +000042#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
wdenk4e112c12003-06-03 23:54:09 +000044#define CONFIG_BAUDRATE 115200 /* console baudrate */
wdenk56f94be2002-11-05 16:35:14 +000045#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
wdenk4e112c12003-06-03 23:54:09 +000048#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
wdenk56f94be2002-11-05 16:35:14 +000049#endif
50
wdenk56f94be2002-11-05 16:35:14 +000051#define CONFIG_BOARD_TYPES 1 /* support board types */
52
wdenk56f94be2002-11-05 16:35:14 +000053
54#undef CONFIG_BOOTARGS
55
wdenk4e112c12003-06-03 23:54:09 +000056
wdenk65faef92004-03-25 19:29:38 +000057#define CONFIG_EXTRA_ENV_SETTINGS \
58"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
59 "run addhw; diskboot 200000 0:1; bootm 200000\0" \
60"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
61 "run addhw; diskboot 200000 2:1; bootm 200000\0" \
62"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \
63"panic_boot=echo No Bootdevice !!! reset\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010064"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
wdenk65faef92004-03-25 19:29:38 +000065"ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010066"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
67 ":${netmask}:${hostname}:${netdev}:off\0" \
68"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
wdenk65faef92004-03-25 19:29:38 +000069"netdev=eth0\0" \
70"contrast=55\0" \
71"silent=1\0" \
72"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010073"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \
wdenke07ec1b2004-05-12 22:54:36 +000074 "cp.b 200000 40050000 14000\0"
wdenk56f94be2002-11-05 16:35:14 +000075
wdenk4e112c12003-06-03 23:54:09 +000076#define CONFIG_BOOTCOMMAND \
77 "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
wdenk56f94be2002-11-05 16:35:14 +000078
wdenk56f94be2002-11-05 16:35:14 +000079
wdenk65faef92004-03-25 19:29:38 +000080#define CONFIG_MISC_INIT_R 1
81#define CONFIG_MISC_INIT_F 1
wdenk56f94be2002-11-05 16:35:14 +000082
83#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
84#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
85
wdenke07ec1b2004-05-12 22:54:36 +000086#define CONFIG_WATCHDOG 1 /* watchdog enabled */
wdenk56f94be2002-11-05 16:35:14 +000087
wdenk65faef92004-03-25 19:29:38 +000088#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenk56f94be2002-11-05 16:35:14 +000089
90#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
91
92#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
93
94#define CONFIG_MAC_PARTITION
95#define CONFIG_DOS_PARTITION
96
wdenk56f94be2002-11-05 16:35:14 +000097
wdenke07ec1b2004-05-12 22:54:36 +000098/*
99 * enable I2C and select the hardware/software driver
100 */
101#undef CONFIG_HARD_I2C /* I2C with hardware support */
102#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
103
104#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
105#define CFG_I2C_SLAVE 0xFE
106
107#ifdef CONFIG_SOFT_I2C
108/*
109 * Software (bit-bang) I2C driver configuration
110 */
111#define PB_SCL 0x00000020 /* PB 26 */
112#define PB_SDA 0x00000010 /* PB 27 */
113
114#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
115#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
116#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
117#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
118#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
119 else immr->im_cpm.cp_pbdat &= ~PB_SDA
120#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
121 else immr->im_cpm.cp_pbdat &= ~PB_SCL
122#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
123#endif /* CONFIG_SOFT_I2C */
124
125
126/*-----------------------------------------------------------------------
127 * I2C Configuration
128 */
129
130#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
131#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
132
wdenk65faef92004-03-25 19:29:38 +0000133
wdenke07ec1b2004-05-12 22:54:36 +0000134/* List of I2C addresses to be verified by POST */
135
136#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \
137 CFG_I2C_RTC_ADDR, \
138 }
139
140
141#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
142
143#define CFG_DISCOVER_PHY
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200144#define CONFIG_MII
wdenke07ec1b2004-05-12 22:54:36 +0000145
146#if 0
147#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
148#endif
149#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */
wdenk56f94be2002-11-05 16:35:14 +0000150
151/* Define to allow the user to overwrite serial and ethaddr */
152#define CONFIG_ENV_OVERWRITE
wdenke07ec1b2004-05-12 22:54:36 +0000153#if 1
154/* POST support */
155
156#define CONFIG_POST (CFG_POST_CPU | \
157 CFG_POST_RTC | \
158 CFG_POST_I2C)
159
160#ifdef CONFIG_POST
161#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
162#else
163#define CFG_CMD_POST_DIAG 0
164#endif
165#endif
wdenk56f94be2002-11-05 16:35:14 +0000166
wdenk56f94be2002-11-05 16:35:14 +0000167
Jon Loeligerb1840de2007-07-08 13:46:18 -0500168/*
169 * Command line configuration.
170 */
171#include <config_cmd_default.h>
172
173#define CONFIG_CMD_DATE
174#define CONFIG_CMD_DHCP
175#define CONFIG_CMD_I2C
176#define CONFIG_CMD_IDE
177#define CONFIG_CMD_NFS
178#define CONFIG_CMD_POST_DIAG
179#define CONFIG_CMD_SNTP
180
wdenk56f94be2002-11-05 16:35:14 +0000181
182/*
183 * Miscellaneous configurable options
184 */
wdenk65faef92004-03-25 19:29:38 +0000185#define CFG_LONGHELP /* undef to save memory */
186#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerb1840de2007-07-08 13:46:18 -0500187#if defined(CONFIG_CMD_KGDB)
wdenk65faef92004-03-25 19:29:38 +0000188#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk56f94be2002-11-05 16:35:14 +0000189#else
wdenk65faef92004-03-25 19:29:38 +0000190#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk56f94be2002-11-05 16:35:14 +0000191#endif
wdenk65faef92004-03-25 19:29:38 +0000192#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
193#define CFG_MAXARGS 16 /* max number of command args */
wdenk56f94be2002-11-05 16:35:14 +0000194#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
195
wdenk65faef92004-03-25 19:29:38 +0000196#define CFG_MEMTEST_START 0x000400000 /* memtest works on */
197#define CFG_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */
wdenk56f94be2002-11-05 16:35:14 +0000198
wdenk65faef92004-03-25 19:29:38 +0000199#define CFG_LOAD_ADDR 0x200000 /* default load address */
wdenk56f94be2002-11-05 16:35:14 +0000200
wdenk65faef92004-03-25 19:29:38 +0000201#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk56f94be2002-11-05 16:35:14 +0000202
wdenk65faef92004-03-25 19:29:38 +0000203#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
wdenk56f94be2002-11-05 16:35:14 +0000204
wdenk4e112c12003-06-03 23:54:09 +0000205#define CFG_CONSOLE_INFO_QUIET 1
206
wdenk56f94be2002-11-05 16:35:14 +0000207/*
208 * Low Level Configuration Settings
209 * (address mappings, register initial values, etc.)
210 * You should know what you are doing if you make changes here.
211 */
212/*-----------------------------------------------------------------------
213 * Internal Memory Mapped Register
214 */
215#define CFG_IMMR 0xFFF00000
216
217/*-----------------------------------------------------------------------
218 * Definitions for initial stack pointer and data area (in DPRAM)
219 */
220#define CFG_INIT_RAM_ADDR CFG_IMMR
wdenk65faef92004-03-25 19:29:38 +0000221#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
222#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
wdenk56f94be2002-11-05 16:35:14 +0000223#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenk65faef92004-03-25 19:29:38 +0000224#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenk56f94be2002-11-05 16:35:14 +0000225
226/*-----------------------------------------------------------------------
227 * Start addresses for the final memory configuration
228 * (Set up by the startup code)
229 * Please note that CFG_SDRAM_BASE _must_ start at 0
230 */
wdenk65faef92004-03-25 19:29:38 +0000231#define CFG_SDRAM_BASE 0x00000000
wdenk56f94be2002-11-05 16:35:14 +0000232#define CFG_FLASH_BASE 0x40000000
wdenk65faef92004-03-25 19:29:38 +0000233#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk56f94be2002-11-05 16:35:14 +0000234#define CFG_MONITOR_BASE CFG_FLASH_BASE
wdenk65faef92004-03-25 19:29:38 +0000235#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk56f94be2002-11-05 16:35:14 +0000236
237/*
238 * For booting Linux, the board info and command line data
239 * have to be in the first 8 MB of memory, since this is
240 * the maximum mapped by the Linux kernel during initialization.
241 */
wdenk65faef92004-03-25 19:29:38 +0000242#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk56f94be2002-11-05 16:35:14 +0000243
244/*-----------------------------------------------------------------------
245 * FLASH organization
246 */
247#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk65faef92004-03-25 19:29:38 +0000248#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
wdenk56f94be2002-11-05 16:35:14 +0000249
250#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
251#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
252
wdenk65faef92004-03-25 19:29:38 +0000253#define CFG_ENV_IS_IN_FLASH 1
wdenke07ec1b2004-05-12 22:54:36 +0000254#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
wdenk65faef92004-03-25 19:29:38 +0000255#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
256#define CFG_ENV_SECT_SIZE 0x10000
wdenk56f94be2002-11-05 16:35:14 +0000257
258/* Address and size of Redundant Environment Sector */
259#if 0
260#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
261#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
262#endif
263/*-----------------------------------------------------------------------
264 * Hardware Information Block
265 */
wdenke07ec1b2004-05-12 22:54:36 +0000266#if 1
267#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
268#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */
269#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
wdenk56f94be2002-11-05 16:35:14 +0000270#endif
271/*-----------------------------------------------------------------------
272 * Cache Configuration
273 */
274#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligerb1840de2007-07-08 13:46:18 -0500275#if defined(CONFIG_CMD_KGDB)
wdenk56f94be2002-11-05 16:35:14 +0000276#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
277#endif
278
279/*-----------------------------------------------------------------------
280 * SYPCR - System Protection Control 11-9
281 * SYPCR can only be written once after reset!
282 *-----------------------------------------------------------------------
283 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
284 */
wdenke07ec1b2004-05-12 22:54:36 +0000285#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
wdenk56f94be2002-11-05 16:35:14 +0000286#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
287 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
288#else
289#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
290#endif
291
292/*-----------------------------------------------------------------------
293 * SIUMCR - SIU Module Configuration 11-6
294 *-----------------------------------------------------------------------
295 * PCMCIA config., multi-function pin tri-state
296 */
297#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
298
299/*-----------------------------------------------------------------------
300 * TBSCR - Time Base Status and Control 11-26
301 *-----------------------------------------------------------------------
302 * Clear Reference Interrupt Status, Timebase freezing enabled
303 */
304#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
305
306/*-----------------------------------------------------------------------
307 * RTCSC - Real-Time Clock Status and Control Register 11-27
308 *-----------------------------------------------------------------------
309 */
310#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
311
312/*-----------------------------------------------------------------------
313 * PISCR - Periodic Interrupt Status and Control 11-31
314 *-----------------------------------------------------------------------
315 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
316 */
317#define CFG_PISCR (PISCR_PS | PISCR_PITF)
318
319/*-----------------------------------------------------------------------
320 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
321 *-----------------------------------------------------------------------
322 * Reset PLL lock status sticky bit, timer expired status bit and timer
323 * interrupt status bit
324 *
325 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
326 */
wdenk4e112c12003-06-03 23:54:09 +0000327#define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
wdenk56f94be2002-11-05 16:35:14 +0000328
329/*-----------------------------------------------------------------------
330 * SCCR - System Clock and reset Control Register 15-27
331 *-----------------------------------------------------------------------
332 * Set clock output, timebase and RTC source and divider,
333 * power management and some other internal clocks
334 */
335#define SCCR_MASK SCCR_EBDF00
wdenk4e112c12003-06-03 23:54:09 +0000336#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \
wdenk56f94be2002-11-05 16:35:14 +0000337 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
338 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
339 SCCR_DFALCD00)
340
341/*-----------------------------------------------------------------------
342 * PCMCIA stuff
343 *-----------------------------------------------------------------------
344 *
345 */
346
wdenk2029f4d2002-11-21 23:11:29 +0000347/* KUP4K use both slots, SLOT_A as "primary". */
wdenk65faef92004-03-25 19:29:38 +0000348#define CONFIG_PCMCIA_SLOT_A 1
wdenk56f94be2002-11-05 16:35:14 +0000349
350#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
351#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
352#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
353#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
354#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
355#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
356#define CFG_PCMCIA_IO_ADDR (0xEC000000)
357#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
358
wdenk2029f4d2002-11-21 23:11:29 +0000359#define PCMCIA_SOCKETS_NO 2
360#define PCMCIA_MEM_WIN_NO 8
wdenk56f94be2002-11-05 16:35:14 +0000361/*-----------------------------------------------------------------------
362 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
363 *-----------------------------------------------------------------------
364 */
365
wdenk65faef92004-03-25 19:29:38 +0000366#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenk56f94be2002-11-05 16:35:14 +0000367
wdenk65faef92004-03-25 19:29:38 +0000368#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
369#define CONFIG_IDE_LED 1 /* LED for ide supported */
wdenk56f94be2002-11-05 16:35:14 +0000370#undef CONFIG_IDE_RESET /* reset for ide not supported */
371
wdenk2029f4d2002-11-21 23:11:29 +0000372#define CFG_IDE_MAXBUS 2
373#define CFG_IDE_MAXDEVICE 4
wdenk56f94be2002-11-05 16:35:14 +0000374
375#define CFG_ATA_IDE0_OFFSET 0x0000
376
wdenk2029f4d2002-11-21 23:11:29 +0000377#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
378
wdenk56f94be2002-11-05 16:35:14 +0000379#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
380
381/* Offset for data I/O */
382#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
383
384/* Offset for normal register accesses */
385#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
386
387/* Offset for alternate registers */
388#define CFG_ATA_ALT_OFFSET 0x0100
389
390
391/*-----------------------------------------------------------------------
392 *
393 *-----------------------------------------------------------------------
394 *
395 */
wdenk65faef92004-03-25 19:29:38 +0000396#define CFG_DER 0
wdenk56f94be2002-11-05 16:35:14 +0000397
398/*
399 * Init Memory Controller:
400 *
401 * BR0/1 and OR0/1 (FLASH)
402 */
403#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
404
405/* used to re-map FLASH both when starting from SRAM or FLASH:
406 * restrict access enough to keep SRAM working (if any)
407 * but not too much to meddle with FLASH accesses
408 */
409#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
410#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
411
412/*
413 * FLASH timing:
414 */
415#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
416 OR_SCY_2_CLK | OR_EHTR | OR_BI)
417
418#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
419#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
420#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
421
422
wdenk56f94be2002-11-05 16:35:14 +0000423/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
424#define CFG_OR_TIMING_SDRAM 0x00000A00
425
wdenk56f94be2002-11-05 16:35:14 +0000426
427/*
428 * Memory Periodic Timer Prescaler
429 *
430 * The Divider for PTA (refresh timer) configuration is based on an
431 * example SDRAM configuration (64 MBit, one bank). The adjustment to
432 * the number of chip selects (NCS) and the actually needed refresh
433 * rate is done by setting MPTPR.
434 *
435 * PTA is calculated from
436 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
437 *
438 * gclk CPU clock (not bus clock!)
439 * Trefresh Refresh cycle * 4 (four word bursts used)
440 *
wdenk65faef92004-03-25 19:29:38 +0000441 * 4096 Rows from SDRAM example configuration
442 * 1000 factor s -> ms
443 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
444 * 4 Number of refresh cycles per period
445 * 64 Refresh cycle in ms per number of rows
wdenk56f94be2002-11-05 16:35:14 +0000446 * --------------------------------------------
447 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
448 *
449 * 50 MHz => 50.000.000 / Divider = 98
450 * 66 Mhz => 66.000.000 / Divider = 129
451 * 80 Mhz => 80.000.000 / Divider = 156
452 */
453#if defined(CONFIG_80MHz)
454#define CFG_MAMR_PTA 156
455#elif defined(CONFIG_66MHz)
456#define CFG_MAMR_PTA 129
457#else /* 50 MHz */
458#define CFG_MAMR_PTA 98
459#endif /*CONFIG_??MHz */
460
461/*
462 * For 16 MBit, refresh rates could be 31.3 us
463 * (= 64 ms / 2K = 125 / quad bursts).
464 * For a simpler initialization, 15.6 us is used instead.
465 *
466 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
467 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
468 */
469#define CFG_MPTPR 0x400
470
471/*
472 * MAMR settings for SDRAM
473 */
474#define CFG_MAMR 0x80802114
475
476/*
477 * Internal Definitions
478 *
479 * Boot Flags
480 */
wdenk65faef92004-03-25 19:29:38 +0000481#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenk56f94be2002-11-05 16:35:14 +0000482#define BOOTFLAG_WARM 0x02 /* Software reboot */
483
484
485#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
486#if 0
487#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
488#endif
wdenk4e112c12003-06-03 23:54:09 +0000489#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
wdenk65faef92004-03-25 19:29:38 +0000490#define CONFIG_SILENT_CONSOLE 1
wdenk56f94be2002-11-05 16:35:14 +0000491
492#endif /* __CONFIG_H */