| Icenowy Zheng | 1259869 | 2018-07-21 16:20:32 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_SUNXI=y |
| Tom Rini | a20e51f | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 3 | CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" |
| Tom Rini | d9669f1 | 2018-08-07 21:40:14 -0400 | [diff] [blame] | 4 | CONFIG_SPL=y |
| Icenowy Zheng | 1259869 | 2018-07-21 16:20:32 +0800 | [diff] [blame] | 5 | CONFIG_MACH_SUN50I_H6=y |
| Andre Przywara | 1c7a751 | 2019-07-15 02:27:06 +0100 | [diff] [blame] | 6 | CONFIG_SUNXI_DRAM_H6_LPDDR3=y |
| Tom Rini | fa94316 | 2020-10-29 10:48:01 -0400 | [diff] [blame] | 7 | CONFIG_MACPWR="PC16" |
| Icenowy Zheng | 1259869 | 2018-07-21 16:20:32 +0800 | [diff] [blame] | 8 | CONFIG_MMC0_CD_PIN="PF6" |
| 9 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 |
| Simon Glass | 4be229d | 2019-07-20 20:51:14 -0600 | [diff] [blame] | 10 | CONFIG_USB3_VBUS_PIN="PL5" |
| Tom Rini | 47dece3 | 2020-04-28 16:15:47 -0400 | [diff] [blame] | 11 | CONFIG_SPL_SPI_SUNXI=y |
| Icenowy Zheng | 1259869 | 2018-07-21 16:20:32 +0800 | [diff] [blame] | 12 | # CONFIG_PSCI_RESET is not set |
| Tom Rini | 8461027 | 2020-07-28 08:46:52 -0400 | [diff] [blame] | 13 | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
| Andre Przywara | 87afc08 | 2022-01-11 12:46:06 +0000 | [diff] [blame] | 14 | CONFIG_SPI_FLASH_WINBOND=y |
| Samuel Holland | 29e506f | 2020-05-07 18:10:52 -0500 | [diff] [blame] | 15 | CONFIG_SUN8I_EMAC=y |
| Samuel Holland | d51c3c9 | 2021-07-05 13:29:04 +0100 | [diff] [blame] | 16 | CONFIG_PHY_SUN50I_USB3=y |
| Andre Przywara | 87afc08 | 2022-01-11 12:46:06 +0000 | [diff] [blame] | 17 | CONFIG_SPI=y |
| Samuel Holland | d51c3c9 | 2021-07-05 13:29:04 +0100 | [diff] [blame] | 18 | CONFIG_USB_XHCI_HCD=y |
| 19 | CONFIG_USB_XHCI_DWC3=y |
| Andre Przywara | 213c297 | 2019-06-23 15:09:50 +0100 | [diff] [blame] | 20 | CONFIG_USB_EHCI_HCD=y |
| 21 | CONFIG_USB_OHCI_HCD=y |
| Samuel Holland | d51c3c9 | 2021-07-05 13:29:04 +0100 | [diff] [blame] | 22 | CONFIG_USB_DWC3=y |
| 23 | # CONFIG_USB_DWC3_GADGET is not set |