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git01.mediatek.com / filogic / uboot / b2d517b73c75d52aad2f460bfab424398cc8bc5e / . / include / configs / omap3_cairo.h
blob: 3030054949f8fdea5228b616bee0811cfb5e667e [file] [log] [blame]
Albert ARIBAUD \(3ADEV\)05e86332015-02-03 18:13:14 +0100[diff] [blame]1/*
2 * Configuration settings for the QUIPOS Cairo board.
3 *
4 * Copyright (C) DENX GmbH
5 *
6 * Author :
7 * Albert ARIBAUD <albert.aribaud@3adev.fr>
8 *
9 * Derived from EVM code by
10 * Manikandan Pillai <mani.pillai@ti.com>
11 * Itself derived from Beagle Board and 3430 SDP code by
12 * Richard Woodruff <r-woodruff2@ti.com>
13 * Syed Mohammed Khasim <khasim@ti.com>
14 *
15 * Also derived from include/configs/omap3_beagle.h
16 *
17 * SPDX-License-Identifier: GPL-2.0+
18 */
19
20#ifndef __OMAP3_CAIRO_CONFIG_H
21#define __OMAP3_CAIRO_CONFIG_H
22
23#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
24
25/*
26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
27 * 64 bytes before this address should be set aside for u-boot.img's
28 * header. That is 0x800FFFC0--0x80100000 should not be used for any
29 * other needs. We use this rather than the inherited defines from
30 * ti_armv7_common.h for backwards compatibility.
31 */
32#define CONFIG_SYS_TEXT_BASE 0x80100000
33#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
34#define CONFIG_SPL_BSS_START_ADDR 0x80000000
35#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
36#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
37#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
38
39#define CONFIG_NAND
40
41#include <configs/ti_omap3_common.h>
42
43/*
44 * Display CPU and Board information
45 */
46#define CONFIG_DISPLAY_CPUINFO 1
47#define CONFIG_DISPLAY_BOARDINFO 1
48
49#define CONFIG_MISC_INIT_R
50
51#define CONFIG_REVISION_TAG 1
52#define CONFIG_ENV_OVERWRITE
53
54/* Enable Multi Bus support for I2C */
55#define CONFIG_I2C_MULTI_BUS 1
56
57/* Probe all devices */
58#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
59
60#define CONFIG_NAND
61
62/* commands to include */
63#include <config_cmd_default.h>
64
65#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
66#define CONFIG_CMD_NAND_LOCK_UNLOCK
67
68/* Disable some commands */
69#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
70#undef CONFIG_CMD_IMI /* iminfo */
71#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
72
73/*
74 * TWL4030
75 */
76#define CONFIG_TWL4030_LED 1
77
78/*
79 * Board NAND Info.
80 */
81#define CONFIG_SYS_NAND_QUIET_TEST 1
82#define CONFIG_NAND_OMAP_GPMC
83#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
84 /* devices */
85/* override default CONFIG_BOOTDELAY */
86#undef CONFIG_BOOTDELAY
87#define CONFIG_BOOTDELAY 0
88
89#define CONFIG_EXTRA_ENV_SETTINGS \
90 "machid=ffffffff\0" \
91 "fdt_high=0x87000000\0" \
92 "baudrate=115200\0" \
93 "ethaddr=00:50:C2:7E:90:F0\0" \
94 "fec_addr=00:50:C2:7E:90:F0\0" \
95 "netmask=255.255.255.0\0" \
96 "ipaddr=192.168.2.9\0" \
97 "gateway=192.168.2.1\0" \
98 "serverip=192.168.2.10\0" \
99 "nfshost=192.168.2.10\0" \
100 "stdin=serial\0" \
101 "stdout=serial\0" \
102 "stderr=serial\0" \
103 "bootargs_mmc_ramdisk=mem=128M " \
104 "console=ttyO1,115200n8 " \
105 "root=/dev/ram0 rw " \
106 "initrd=0x81600000,16M " \
107 "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
108 "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
109 "mmcboot=mmc init; " \
110 "fatload mmc 0 0x80000000 uImage; " \
111 "fatload mmc 0 0x81600000 ramdisk.gz; " \
112 "setenv bootargs ${bootargs_mmc_ramdisk}; " \
113 "bootm 0x80000000\0" \
114 "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
115 "root=/dev/nfs " \
116 "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
117 "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
118 "omap_vout.vid1_static_vrfb_alloc=y\0" \
119 "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
120 "bootm 0x80000000\0" \
121 "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
122 "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
123 "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
124 "omapfb.rotate_type=1\0" \
125 "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
126 "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
127 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
128 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
129 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
130 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
131 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
132 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
133 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
134 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
135 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
136 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
137 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
138 "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
139 "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
140 "nand erase 0 20000; " \
141 "fatload mmc 0 0x81600000 MLO; " \
142 "nandecc hw; " \
143 "nand write.i 0x81600000 0 20000;\0" \
144 "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
145 "nand erase 80000 40000; " \
146 "fatload mmc 0 0x81600000 u-boot.bin; " \
147 "nandecc sw; " \
148 "nand write.i 0x81600000 80000 40000;\0" \
149 "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
150 "nand erase 280000 300000; " \
151 "fatload mmc 0 0x81600000 uImage; " \
152 "nandecc sw; " \
153 "nand write.i 0x81600000 280000 300000;\0" \
154 "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
155 "nandecc sw; " \
156 "nand write.jffs2 0x680000 0xFF ${filesize}; " \
157 "nand erase 680000 ${filesize}; " \
158 "nand write.jffs2 81600000 680000 ${filesize};\0" \
159 "flash_scrub=nand scrub; " \
160 "run flash_xloader; " \
161 "run flash_uboot; " \
162 "run flash_kernel; " \
163 "run flash_rootfs;\0" \
164 "flash_all=run ledred; " \
165 "nand erase.chip; " \
166 "run ledorange; " \
167 "run flash_xloader; " \
168 "run flash_uboot; " \
169 "run flash_kernel; " \
170 "run flash_rootfs; " \
171 "run ledgreen; " \
172 "run boot_nand; \0" \
173
174#define CONFIG_BOOTCOMMAND \
175 "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
176 "else run boot_nand; fi"
177
178/*
179 * OMAP3 has 12 GP timers, they can be driven by the system clock
180 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
181 * This rate is divided by a local divisor.
182 */
183#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
184
185/*-----------------------------------------------------------------------
186 * FLASH and environment organization
187 */
188
189/* **** PISMO SUPPORT *** */
190#if defined(CONFIG_CMD_NAND)
191#define CONFIG_SYS_FLASH_BASE NAND_BASE
192#endif
193
194/* Monitor at start of flash */
195#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
196#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
197
198#define CONFIG_ENV_IS_IN_NAND 1
199#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
200#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
201#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
202
203#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
204#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
205#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
206
207#define CONFIG_OMAP3_SPI
208
209#define CONFIG_SYS_CACHELINE_SIZE 64
210
211/* Defines for SPL */
212#define CONFIG_SPL_OMAP3_ID_NAND
213
214/* NAND boot config */
215#define CONFIG_SYS_NAND_5_ADDR_CYCLE
216#define CONFIG_SYS_NAND_PAGE_COUNT 64
217#define CONFIG_SYS_NAND_PAGE_SIZE 2048
218#define CONFIG_SYS_NAND_OOBSIZE 64
219#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
220#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
221#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
222 10, 11, 12, 13}
223#define CONFIG_SYS_NAND_ECCSIZE 512
224#define CONFIG_SYS_NAND_ECCBYTES 3
225#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
226#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
227/* NAND: SPL falcon mode configs */
228#ifdef CONFIG_SPL_OS_BOOT
229#define CONFIG_CMD_SPL_NAND_OFS 0x240000
230#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
231#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
232#endif
233
234/* env defaults */
235#define CONFIG_BOOTFILE "uImage"
236
237/* Override OMAP3 common serial console configuration from UART3
238 * to UART2.
239 *
240 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
241 * are needed and peripheral clocks for UART2 must be enabled in
242 * function per_clocks_enable().
243 */
244#undef CONFIG_CONS_INDEX
245#define CONFIG_CONS_INDEX 2
246#ifdef CONFIG_SPL_BUILD
247#undef CONFIG_SYS_NS16550_COM3
248#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
249#undef CONFIG_SERIAL3
250#define CONFIG_SERIAL2
251#endif
252
253/* Keep old prompt in case some existing script depends on it */
254#undef CONFIG_SYS_PROMPT
255#define CONFIG_SYS_PROMPT "Cairo # "
256
257/* Provide MACH_TYPE for compatibility with non-DT kernels */
258#define MACH_TYPE_OMAP3_CAIRO 3063
259#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
260
261/*-----------------------------------------------------------------------
262 * FLASH and environment organization
263 */
264
265/* **** PISMO SUPPORT *** */
266
267#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
268 /* on one chip */
269#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
270
271/*-----------------------------------------------------------------------
272 * CFI FLASH driver setup
273 */
274/* timeout values are in ticks */
275#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
276#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
277
278/* Flash banks JFFS2 should use */
279#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
280 CONFIG_SYS_MAX_NAND_DEVICE)
281#define CONFIG_SYS_JFFS2_MEM_NAND
282/* use flash_info[2] */
283#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
284#define CONFIG_SYS_JFFS2_NUM_BANKS 1
285
286#endif /* __OMAP3_CAIRO_CONFIG_H */