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git01.mediatek.com / filogic / uboot / eaef1296a742e4b09711fa1d75709154ce264e1f / . / arch / arm / mach-k3 / am642_init.c
blob: aa0eb72a870926148e33f24fce589f0ce7bbeacf [file] [log] [blame]
Dave Gerlach96571ec2021-04-23 11:27:32 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM642: SoC specific initialization
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 * Keerthy <j-keerthy@ti.com>
7 * Dave Gerlach <d-gerlach@ti.com>
8 */
9
10#include <common.h>
11#include <spl.h>
12#include <asm/io.h>
Keerthy05d670e2021-04-23 11:27:33 -0500[diff] [blame]13#include <asm/arch/hardware.h>
Dave Gerlach96571ec2021-04-23 11:27:32 -0500[diff] [blame]14#include "common.h"
15
16#if defined(CONFIG_SPL_BUILD)
17
Dave Gerlacheaef1292021-04-23 11:27:34 -0500[diff] [blame^]18static void ctrl_mmr_unlock(void)
19{
20 /* Unlock all PADCFG_MMR1 module registers */
21 mmr_unlock(PADCFG_MMR1_BASE, 1);
22
23 /* Unlock all CTRL_MMR0 module registers */
24 mmr_unlock(CTRL_MMR0_BASE, 0);
25 mmr_unlock(CTRL_MMR0_BASE, 1);
26 mmr_unlock(CTRL_MMR0_BASE, 2);
27 mmr_unlock(CTRL_MMR0_BASE, 3);
28 mmr_unlock(CTRL_MMR0_BASE, 5);
29 mmr_unlock(CTRL_MMR0_BASE, 6);
30}
31
Dave Gerlach96571ec2021-04-23 11:27:32 -0500[diff] [blame]32void board_init_f(ulong dummy)
33{
34#if defined(CONFIG_CPU_V7R)
35 setup_k3_mpu_regions();
36#endif
37
Dave Gerlacheaef1292021-04-23 11:27:34 -0500[diff] [blame^]38 ctrl_mmr_unlock();
39
Dave Gerlach96571ec2021-04-23 11:27:32 -0500[diff] [blame]40 /* Init DM early */
41 spl_early_init();
42
43 preloader_console_init();
44}
Keerthy05d670e2021-04-23 11:27:33 -0500[diff] [blame]45
46u32 spl_boot_mode(const u32 boot_device)
47{
48 switch (boot_device) {
49 case BOOT_DEVICE_MMC1:
50 return MMCSD_MODE_EMMCBOOT;
51
52 case BOOT_DEVICE_MMC2:
53 return MMCSD_MODE_FS;
54
55 default:
56 return MMCSD_MODE_RAW;
57 }
58}
59
60static u32 __get_backup_bootmedia(u32 main_devstat)
61{
62 u32 bkup_bootmode =
63 (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
64 MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
65 u32 bkup_bootmode_cfg =
66 (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
67 MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
68
69 switch (bkup_bootmode) {
70 case BACKUP_BOOT_DEVICE_UART:
71 return BOOT_DEVICE_UART;
72
73 case BACKUP_BOOT_DEVICE_USB:
74 return BOOT_DEVICE_USB;
75
76 case BACKUP_BOOT_DEVICE_ETHERNET:
77 return BOOT_DEVICE_ETHERNET;
78
79 case BACKUP_BOOT_DEVICE_MMC:
80 if (bkup_bootmode_cfg)
81 return BOOT_DEVICE_MMC2;
82 return BOOT_DEVICE_MMC1;
83
84 case BACKUP_BOOT_DEVICE_SPI:
85 return BOOT_DEVICE_SPI;
86
87 case BACKUP_BOOT_DEVICE_I2C:
88 return BOOT_DEVICE_I2C;
89 };
90
91 return BOOT_DEVICE_RAM;
92}
93
94static u32 __get_primary_bootmedia(u32 main_devstat)
95{
96 u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
97 MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
98 u32 bootmode_cfg =
99 (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
100 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
101
102 switch (bootmode) {
103 case BOOT_DEVICE_OSPI:
104 fallthrough;
105 case BOOT_DEVICE_QSPI:
106 fallthrough;
107 case BOOT_DEVICE_XSPI:
108 fallthrough;
109 case BOOT_DEVICE_SPI:
110 return BOOT_DEVICE_SPI;
111
112 case BOOT_DEVICE_ETHERNET_RGMII:
113 fallthrough;
114 case BOOT_DEVICE_ETHERNET_RMII:
115 return BOOT_DEVICE_ETHERNET;
116
117 case BOOT_DEVICE_EMMC:
118 return BOOT_DEVICE_MMC1;
119
120 case BOOT_DEVICE_MMC:
121 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
122 MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
123 return BOOT_DEVICE_MMC2;
124 return BOOT_DEVICE_MMC1;
125
126 case BOOT_DEVICE_NOBOOT:
127 return BOOT_DEVICE_RAM;
128 }
129
130 return bootmode;
131}
132
133u32 spl_boot_device(void)
134{
135 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
136
137 if (bootindex == K3_PRIMARY_BOOTMODE)
138 return __get_primary_bootmedia(devstat);
139 else
140 return __get_backup_bootmedia(devstat);
141}
Dave Gerlach96571ec2021-04-23 11:27:32 -0500[diff] [blame]142#endif