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git01.mediatek.com / filogic / uboot / 179dd643c15c6d998bb5efbbd9d59271799d9bb8 / . / board / iomega / iconnect / iconnect.c
blob: 9e123aab0023972d9d593c0e55a83e380dfa86f8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]2/*
3 * Copyright (C) 2009-2012
4 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
Luka Perkove91505d2012-12-03 03:24:15 +0000[diff] [blame]5 * Luka Perkov <luka@openwrt.org>
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]6 */
7
8#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]9#include <init.h>
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]10#include <miiphy.h>
11#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]12#include <asm/arch/soc.h>
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]13#include <asm/arch/mpp.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]14#include <asm/global_data.h>
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]15#include "iconnect.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19int board_early_init_f(void)
20{
21 /*
22 * default gpio configuration
23 * There are maximum 64 gpios controlled through 2 sets of registers
24 * the below configuration configures mainly initial LED status
25 */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]26 mvebu_config_gpio(ICONNECT_OE_VAL_LOW,
27 ICONNECT_OE_VAL_HIGH,
28 ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]29
30 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]31 static const u32 kwmpp_config[] = {
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]32 MPP0_NF_IO2,
33 MPP1_NF_IO3,
34 MPP2_NF_IO4,
35 MPP3_NF_IO5,
36 MPP4_NF_IO6,
37 MPP5_NF_IO7,
38 MPP6_SYSRST_OUTn, /* Reset signal */
39 MPP7_GPO,
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]40 MPP8_TW_SDA, /* I2C */
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]41 MPP9_TW_SCK, /* I2C */
42 MPP10_UART0_TXD,
43 MPP11_UART0_RXD,
44 MPP12_GPO, /* Reset button */
45 MPP13_SD_CMD,
46 MPP14_SD_D0,
47 MPP15_SD_D1,
48 MPP16_SD_D2,
49 MPP17_SD_D3,
50 MPP18_NF_IO0,
51 MPP19_NF_IO1,
52 MPP20_GE1_0,
53 MPP21_GE1_1,
54 MPP22_GE1_2,
55 MPP23_GE1_3,
56 MPP24_GE1_4,
57 MPP25_GE1_5,
58 MPP26_GE1_6,
59 MPP27_GE1_7,
60 MPP28_GPIO,
61 MPP29_GPIO,
62 MPP30_GE1_10,
63 MPP31_GE1_11,
64 MPP32_GE1_12,
65 MPP33_GE1_13,
66 MPP34_GE1_14,
67 MPP35_GPIO, /* OTB button */
68 MPP36_AUDIO_SPDIFI,
69 MPP37_AUDIO_SPDIFO,
70 MPP38_GPIO,
71 MPP39_TDM_SPI_CS0,
72 MPP40_TDM_SPI_SCK,
73 MPP41_GPIO, /* LED brightness */
74 MPP42_GPIO, /* LED power (blue) */
75 MPP43_GPIO, /* LED power (red) */
76 MPP44_GPIO, /* LED USB 1 */
77 MPP45_GPIO, /* LED USB 2 */
78 MPP46_GPIO, /* LED USB 3 */
79 MPP47_GPIO, /* LED USB 4 */
80 MPP48_GPIO, /* LED OTB */
81 MPP49_GPIO,
82 0
83 };
84 kirkwood_mpp_conf(kwmpp_config, NULL);
85 return 0;
86}
87
88int board_init(void)
89{
90 /* adress of boot parameters */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]91 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Luka Perkov9f497062012-09-05 08:01:25 +0000[diff] [blame]92
93 return 0;
94}
Tony Dinh94142cc2022-01-01 20:57:38 -0800[diff] [blame]95
96int board_late_init(void)
97{
98 /* Do late init to ensure successful enumeration of PCIe devices */
99 pci_init();
100 return 0;
101}