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git01.mediatek.com / filogic / uboot / b20a50628f171f1b80b66971478e8d3e14833d92 / . / include / configs / cm-bf527.h
blob: e9e4e1414a942ab9d81cc9138f81c0c339193b94 [file] [log] [blame]
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]1/*
2 * U-boot - Configuration file for CM-BF527 board
3 */
4
5#ifndef __CONFIG_CM_BF527_H__
6#define __CONFIG_CM_BF527_H__
7
Mike Frysinger18a407c2009-04-24 17:22:40 -0400[diff] [blame]8#include <asm/config-pre.h>
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]9
10
11/*
12 * Processor Settings
13 */
Mike Frysinger5b0c1282010-12-23 14:58:37 -0500[diff] [blame]14#define CONFIG_BFIN_CPU bf527-0.0
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 21
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
Harald Krapfenbauer2bdd9192009-10-14 08:37:32 -0400[diff] [blame]41/* Decrease core voltage */
42#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000)
43
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]44
45/*
46 * Memory Settings
47 */
48#define CONFIG_MEM_ADD_WDTH 9
49#define CONFIG_MEM_SIZE 32
50
51#define CONFIG_EBIU_SDRRC_VAL 0x3f8
52#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
53
54#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
55#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
56#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
57
58#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
59#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
60
61
62/*
63 * NAND Settings
64 * (can't be used sametime as ethernet)
65 */
66/* #define CONFIG_BFIN_NFC */
67#ifdef CONFIG_BFIN_NFC
68#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
69#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
70#define CONFIG_SYS_MAX_NAND_DEVICE 1
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]71#define CONFIG_CMD_NAND
72#endif
73
74
75/*
76 * Network Settings
77 */
78#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
79 !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
80#define ADI_CMDS_NETWORK 1
81#define CONFIG_BFIN_MAC
82#define CONFIG_RMII
83#define CONFIG_NETCONSOLE 1
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]84#endif
85#define CONFIG_HOSTNAME cm-bf527
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]86
87/*
88 * Flash Settings
89 */
90#define CONFIG_FLASH_CFI_DRIVER
91#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
92#define CONFIG_SYS_FLASH_BASE 0x20000000
93#define CONFIG_SYS_FLASH_CFI
94#define CONFIG_SYS_FLASH_PROTECTION
95#define CONFIG_SYS_MAX_FLASH_BANKS 1
Harald Krapfenbauerb46c3472009-08-18 04:49:57 -0400[diff] [blame]96#define CONFIG_SYS_MAX_FLASH_SECT 67
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]97
98
99/*
100 * Env Storage Settings
101 */
102#define CONFIG_ENV_IS_IN_FLASH 1
103#define CONFIG_ENV_ADDR 0x20008000
104#define CONFIG_ENV_OFFSET 0x8000
105#define CONFIG_ENV_SIZE 0x8000
Harald Krapfenbauer2bdd9192009-10-14 08:37:32 -0400[diff] [blame]106#define CONFIG_ENV_SECT_SIZE 0x8000
Mike Frysinger45b57bd2009-07-21 22:17:36 -0400[diff] [blame]107#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]108
109
110/*
111 * I2C Settings
112 */
Scott Jiang80d27fa2014-11-13 15:30:55 +0800[diff] [blame]113#define CONFIG_SYS_I2C
Scott Jiang655761e2014-11-13 15:30:53 +0800[diff] [blame]114#define CONFIG_SYS_I2C_ADI
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]115
116
117/*
118 * Misc Settings
119 */
120#define CONFIG_BAUDRATE 115200
121#define CONFIG_MISC_INIT_R
122#define CONFIG_RTC_BFIN
123#define CONFIG_UART_CONSOLE 0
Harald Krapfenbauer2bdd9192009-10-14 08:37:32 -0400[diff] [blame]124#define CONFIG_BOOTCOMMAND "run flashboot"
125#define FLASHBOOT_ENV_SETTINGS \
126 "flashboot=flread 20040000 1000000 300000;" \
127 "bootm 0x1000000\0"
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]128
129/*
130 * Pull in common ADI header for remaining command/environment setup
131 */
132#include <configs/bfin_adi_common.h>
133
Mike Frysinger07f82272008-10-12 21:55:45 -0400[diff] [blame]134#endif