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git01.mediatek.com / filogic / uboot / b1eed71ceba40a77eca1493022a5b5c10d96dea4 / . / drivers / clk / mediatek / clk-mt8516.c
blob: 623f88499f1b0be2bd2b832d70cd10565eadfe18 [file] [log] [blame]
Fabien Parent1fe5ad02019-03-24 16:46:36 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek clock driver for MT8516 SoC
4 *
5 * Copyright (C) 2018 BayLibre, SAS
6 * Author: Fabien Parent <fparent@baylibre.com>
7 */
8
Fabien Parent1fe5ad02019-03-24 16:46:36 +0100[diff] [blame]9#include <dm.h>
10#include <asm/io.h>
11#include <dt-bindings/clock/mt8516-clk.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]12#include <linux/bitops.h>
Fabien Parent1fe5ad02019-03-24 16:46:36 +0100[diff] [blame]13
14#include "clk-mtk.h"
15
16#define MT8516_PLL_FMAX (1502UL * MHZ)
17#define MT8516_CON0_RST_BAR BIT(27)
18
19/* apmixedsys */
20#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
21 _pd_shift, _pcw_reg, _pcw_shift) { \
22 .id = _id, \
23 .reg = _reg, \
24 .pwr_reg = _pwr_reg, \
25 .en_mask = _en_mask, \
26 .rst_bar_mask = MT8516_CON0_RST_BAR, \
27 .fmax = MT8516_PLL_FMAX, \
28 .flags = _flags, \
29 .pcwbits = _pcwbits, \
30 .pd_reg = _pd_reg, \
31 .pd_shift = _pd_shift, \
32 .pcw_reg = _pcw_reg, \
33 .pcw_shift = _pcw_shift, \
34 }
35
36static const struct mtk_pll_data apmixed_plls[] = {
37 PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
38 21, 0x0104, 24, 0x0104, 0),
39 PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
40 HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
41 PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
42 HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
43 PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
44 21, 0x0164, 24, 0x0164, 0),
45 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
46 31, 0x0180, 1, 0x0184, 0),
47 PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
48 31, 0x01A0, 1, 0x01A4, 0),
49};
50
51/* topckgen */
52#define FACTOR0(_id, _parent, _mult, _div) \
53 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
54
55#define FACTOR1(_id, _parent, _mult, _div) \
56 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
57
58#define FACTOR2(_id, _parent, _mult, _div) \
59 FACTOR(_id, _parent, _mult, _div, 0)
60
61static const struct mtk_fixed_clk top_fixed_clks[] = {
62 FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
63 FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
64 FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
65};
66
67static const struct mtk_fixed_factor top_fixed_divs[] = {
68 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
69 FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
70 FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
71 FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
72 FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
73 FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
74 FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
75 FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
76 FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
77 FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
78 FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
79 FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
80 FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
81 FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
82 FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
83 FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
84 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
85 FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
86 FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
87 FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
88 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
89 FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
90 FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
91 FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
92 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
93 FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
94 FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
95 FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
96 FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
97 FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
98 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
99 FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
100 FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
101 FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
102 FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
103 FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
104 FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
105 FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
106 FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
107 FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
108 FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
109 FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
110 FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
111};
112
113static const int uart0_parents[] = {
114 CLK_TOP_CLK26M,
115 CLK_TOP_UNIVPLL_D24,
116};
117
118static const int gfmux_emi1x_parents[] = {
119 CLK_TOP_CLK26M,
120 CLK_TOP_DMPLL,
121};
122
123static const int emi_ddrphy_parents[] = {
124 CLK_TOP_GFMUX_EMI1X_SEL,
125 CLK_TOP_GFMUX_EMI1X_SEL,
126};
127
128static const int ahb_infra_parents[] = {
129 CLK_TOP_CLK_NULL,
130 CLK_TOP_CLK26M,
131 CLK_TOP_MAINPLL_D11,
132 CLK_TOP_CLK_NULL,
133 CLK_TOP_MAINPLL_D12,
134 CLK_TOP_CLK_NULL,
135 CLK_TOP_CLK_NULL,
136 CLK_TOP_CLK_NULL,
137 CLK_TOP_CLK_NULL,
138 CLK_TOP_CLK_NULL,
139 CLK_TOP_CLK_NULL,
140 CLK_TOP_CLK_NULL,
141 CLK_TOP_MAINPLL_D10,
142};
143
144static const int csw_mux_mfg_parents[] = {
145 CLK_TOP_CLK_NULL,
146 CLK_TOP_CLK_NULL,
147 CLK_TOP_UNIVPLL_D3,
148 CLK_TOP_UNIVPLL_D2,
149 CLK_TOP_CLK26M,
150 CLK_TOP_MAINPLL_D4,
151 CLK_TOP_UNIVPLL_D24,
152 CLK_TOP_MMPLL380M,
153};
154
155static const int msdc0_parents[] = {
156 CLK_TOP_CLK26M,
157 CLK_TOP_UNIVPLL_D6,
158 CLK_TOP_MAINPLL_D8,
159 CLK_TOP_UNIVPLL_D8,
160 CLK_TOP_MAINPLL_D16,
161 CLK_TOP_MMPLL_200M,
162 CLK_TOP_MAINPLL_D12,
163 CLK_TOP_MMPLL_D2,
164};
165
166static const int pwm_mm_parents[] = {
167 CLK_TOP_CLK26M,
168 CLK_TOP_UNIVPLL_D12,
169};
170
171static const int uart1_parents[] = {
172 CLK_TOP_CLK26M,
173 CLK_TOP_UNIVPLL_D24,
174};
175
176static const int msdc1_parents[] = {
177 CLK_TOP_CLK26M,
178 CLK_TOP_UNIVPLL_D6,
179 CLK_TOP_MAINPLL_D8,
180 CLK_TOP_UNIVPLL_D8,
181 CLK_TOP_MAINPLL_D16,
182 CLK_TOP_MMPLL_200M,
183 CLK_TOP_MAINPLL_D12,
184 CLK_TOP_MMPLL_D2,
185};
186
187static const int spm_52m_parents[] = {
188 CLK_TOP_CLK26M,
189 CLK_TOP_UNIVPLL_D24,
190};
191
192static const int pmicspi_parents[] = {
193 CLK_TOP_UNIVPLL_D20,
194 CLK_TOP_USB_PHY48M,
195 CLK_TOP_UNIVPLL_D16,
196 CLK_TOP_CLK26M,
197};
198
199static const int qaxi_aud26m_parents[] = {
200 CLK_TOP_CLK26M,
201 CLK_TOP_AHB_INFRA_SEL,
202};
203
204static const int aud_intbus_parents[] = {
205 CLK_TOP_CLK_NULL,
206 CLK_TOP_CLK26M,
207 CLK_TOP_MAINPLL_D22,
208 CLK_TOP_CLK_NULL,
209 CLK_TOP_MAINPLL_D11,
210};
211
212static const int nfi2x_pad_parents[] = {
213 CLK_TOP_CLK_NULL,
214 CLK_TOP_CLK_NULL,
215 CLK_TOP_CLK_NULL,
216 CLK_TOP_CLK_NULL,
217 CLK_TOP_CLK_NULL,
218 CLK_TOP_CLK_NULL,
219 CLK_TOP_CLK_NULL,
220 CLK_TOP_CLK_NULL,
221 CLK_TOP_CLK26M,
222 CLK_TOP_CLK_NULL,
223 CLK_TOP_CLK_NULL,
224 CLK_TOP_CLK_NULL,
225 CLK_TOP_CLK_NULL,
226 CLK_TOP_CLK_NULL,
227 CLK_TOP_CLK_NULL,
228 CLK_TOP_CLK_NULL,
229 CLK_TOP_CLK_NULL,
230 CLK_TOP_MAINPLL_D12,
231 CLK_TOP_MAINPLL_D8,
232 CLK_TOP_CLK_NULL,
233 CLK_TOP_MAINPLL_D6,
234 CLK_TOP_CLK_NULL,
235 CLK_TOP_CLK_NULL,
236 CLK_TOP_CLK_NULL,
237 CLK_TOP_CLK_NULL,
238 CLK_TOP_CLK_NULL,
239 CLK_TOP_CLK_NULL,
240 CLK_TOP_CLK_NULL,
241 CLK_TOP_CLK_NULL,
242 CLK_TOP_CLK_NULL,
243 CLK_TOP_CLK_NULL,
244 CLK_TOP_CLK_NULL,
245 CLK_TOP_MAINPLL_D4,
246 CLK_TOP_CLK_NULL,
247 CLK_TOP_CLK_NULL,
248 CLK_TOP_CLK_NULL,
249 CLK_TOP_CLK_NULL,
250 CLK_TOP_CLK_NULL,
251 CLK_TOP_CLK_NULL,
252 CLK_TOP_CLK_NULL,
253 CLK_TOP_CLK_NULL,
254 CLK_TOP_CLK_NULL,
255 CLK_TOP_CLK_NULL,
256 CLK_TOP_CLK_NULL,
257 CLK_TOP_CLK_NULL,
258 CLK_TOP_CLK_NULL,
259 CLK_TOP_CLK_NULL,
260 CLK_TOP_CLK_NULL,
261 CLK_TOP_CLK_NULL,
262 CLK_TOP_CLK_NULL,
263 CLK_TOP_CLK_NULL,
264 CLK_TOP_CLK_NULL,
265 CLK_TOP_CLK_NULL,
266 CLK_TOP_CLK_NULL,
267 CLK_TOP_CLK_NULL,
268 CLK_TOP_CLK_NULL,
269 CLK_TOP_CLK_NULL,
270 CLK_TOP_CLK_NULL,
271 CLK_TOP_CLK_NULL,
272 CLK_TOP_CLK_NULL,
273 CLK_TOP_CLK_NULL,
274 CLK_TOP_CLK_NULL,
275 CLK_TOP_CLK_NULL,
276 CLK_TOP_CLK_NULL,
277 CLK_TOP_CLK_NULL,
278 CLK_TOP_CLK_NULL,
279 CLK_TOP_CLK_NULL,
280 CLK_TOP_CLK_NULL,
281 CLK_TOP_CLK_NULL,
282 CLK_TOP_CLK_NULL,
283 CLK_TOP_CLK_NULL,
284 CLK_TOP_CLK_NULL,
285 CLK_TOP_CLK_NULL,
286 CLK_TOP_CLK_NULL,
287 CLK_TOP_CLK_NULL,
288 CLK_TOP_CLK_NULL,
289 CLK_TOP_CLK_NULL,
290 CLK_TOP_CLK_NULL,
291 CLK_TOP_CLK_NULL,
292 CLK_TOP_CLK_NULL,
293 CLK_TOP_CLK_NULL,
294 CLK_TOP_MAINPLL_D10,
295 CLK_TOP_MAINPLL_D7,
296 CLK_TOP_CLK_NULL,
297 CLK_TOP_MAINPLL_D5
298};
299
300static const int nfi1x_pad_parents[] = {
301 CLK_TOP_AHB_INFRA_SEL,
302 CLK_TOP_NFI1X,
303};
304
305static const int mfg_mm_parents[] = {
306 CLK_TOP_CLK_NULL,
307 CLK_TOP_CLK_NULL,
308 CLK_TOP_CLK_NULL,
309 CLK_TOP_CLK_NULL,
310 CLK_TOP_CLK_NULL,
311 CLK_TOP_CLK_NULL,
312 CLK_TOP_CLK_NULL,
313 CLK_TOP_CLK_NULL,
314 CLK_TOP_CSW_MUX_MFG_SEL,
315 CLK_TOP_CLK_NULL,
316 CLK_TOP_CLK_NULL,
317 CLK_TOP_CLK_NULL,
318 CLK_TOP_CLK_NULL,
319 CLK_TOP_CLK_NULL,
320 CLK_TOP_CLK_NULL,
321 CLK_TOP_CLK_NULL,
322 CLK_TOP_MAINPLL_D3,
323 CLK_TOP_CLK_NULL,
324 CLK_TOP_CLK_NULL,
325 CLK_TOP_CLK_NULL,
326 CLK_TOP_CLK_NULL,
327 CLK_TOP_CLK_NULL,
328 CLK_TOP_CLK_NULL,
329 CLK_TOP_CLK_NULL,
330 CLK_TOP_CLK_NULL,
331 CLK_TOP_CLK_NULL,
332 CLK_TOP_CLK_NULL,
333 CLK_TOP_CLK_NULL,
334 CLK_TOP_CLK_NULL,
335 CLK_TOP_CLK_NULL,
336 CLK_TOP_CLK_NULL,
337 CLK_TOP_CLK_NULL,
338 CLK_TOP_CLK_NULL,
339 CLK_TOP_MAINPLL_D5,
340 CLK_TOP_MAINPLL_D7,
341 CLK_TOP_CLK_NULL,
342 CLK_TOP_MAINPLL_D14
343};
344
345static const int ddrphycfg_parents[] = {
346 CLK_TOP_CLK26M,
347 CLK_TOP_MAINPLL_D16
348};
349
350static const int usb_78m_parents[] = {
351 CLK_TOP_CLK_NULL,
352 CLK_TOP_CLK26M,
353 CLK_TOP_UNIVPLL_D16,
354 CLK_TOP_CLK_NULL,
355 CLK_TOP_MAINPLL_D20,
356};
357
358static const int spinor_parents[] = {
359 CLK_TOP_CLK26M_D2,
360 CLK_TOP_CLK26M,
361 CLK_TOP_MAINPLL_D40,
362 CLK_TOP_UNIVPLL_D24,
363 CLK_TOP_UNIVPLL_D20,
364 CLK_TOP_MAINPLL_D20,
365 CLK_TOP_MAINPLL_D16,
366 CLK_TOP_UNIVPLL_D12
367};
368
369static const int msdc2_parents[] = {
370 CLK_TOP_CLK26M,
371 CLK_TOP_UNIVPLL_D6,
372 CLK_TOP_MAINPLL_D8,
373 CLK_TOP_UNIVPLL_D8,
374 CLK_TOP_MAINPLL_D16,
375 CLK_TOP_MMPLL_200M,
376 CLK_TOP_MAINPLL_D12,
377 CLK_TOP_MMPLL_D2
378};
379
380static const int eth_parents[] = {
381 CLK_TOP_CLK26M,
382 CLK_TOP_MAINPLL_D40,
383 CLK_TOP_UNIVPLL_D24,
384 CLK_TOP_UNIVPLL_D20,
385 CLK_TOP_MAINPLL_D20
386};
387
388static const int axi_mfg_in_parents[] = {
389 CLK_TOP_CLK26M,
390 CLK_TOP_MAINPLL_D11,
391 CLK_TOP_UNIVPLL_D24,
392 CLK_TOP_MMPLL380M,
393};
394
395static const int slow_mfg_parents[] = {
396 CLK_TOP_CLK26M,
397 CLK_TOP_UNIVPLL_D12,
398 CLK_TOP_UNIVPLL_D24
399};
400
401static const int aud1_parents[] = {
402 CLK_TOP_CLK26M,
403 CLK_TOP_APLL1
404};
405
406static const int aud2_parents[] = {
407 CLK_TOP_CLK26M,
408 CLK_TOP_APLL2
409};
410
411static const int aud_engen1_parents[] = {
412 CLK_TOP_CLK26M,
413 CLK_TOP_RG_APLL1_D2_EN,
414 CLK_TOP_RG_APLL1_D4_EN,
415 CLK_TOP_RG_APLL1_D8_EN
416};
417
418static const int aud_engen2_parents[] = {
419 CLK_TOP_CLK26M,
420 CLK_TOP_RG_APLL2_D2_EN,
421 CLK_TOP_RG_APLL2_D4_EN,
422 CLK_TOP_RG_APLL2_D8_EN
423};
424
425static const int i2c_parents[] = {
426 CLK_TOP_CLK26M,
427 CLK_TOP_UNIVPLL_D20,
428 CLK_TOP_UNIVPLL_D16,
429 CLK_TOP_UNIVPLL_D12
430};
431
432static const int aud_i2s0_m_parents[] = {
433 CLK_TOP_RG_AUD1,
434 CLK_TOP_RG_AUD2
435};
436
437static const int pwm_parents[] = {
438 CLK_TOP_CLK26M,
439 CLK_TOP_UNIVPLL_D12
440};
441
442static const int spi_parents[] = {
443 CLK_TOP_CLK26M,
444 CLK_TOP_UNIVPLL_D12,
445 CLK_TOP_UNIVPLL_D8,
446 CLK_TOP_UNIVPLL_D6
447};
448
449static const int aud_spdifin_parents[] = {
450 CLK_TOP_CLK26M,
451 CLK_TOP_UNIVPLL_D2
452};
453
454static const int uart2_parents[] = {
455 CLK_TOP_CLK26M,
456 CLK_TOP_UNIVPLL_D24
457};
458
459static const int bsi_parents[] = {
460 CLK_TOP_CLK26M,
461 CLK_TOP_MAINPLL_D10,
462 CLK_TOP_MAINPLL_D12,
463 CLK_TOP_MAINPLL_D20
464};
465
466static const int dbg_atclk_parents[] = {
467 CLK_TOP_CLK_NULL,
468 CLK_TOP_CLK26M,
469 CLK_TOP_MAINPLL_D5,
470 CLK_TOP_CLK_NULL,
471 CLK_TOP_UNIVPLL_D5
472};
473
474static const int csw_nfiecc_parents[] = {
475 CLK_TOP_CLK_NULL,
476 CLK_TOP_MAINPLL_D7,
477 CLK_TOP_MAINPLL_D6,
478 CLK_TOP_CLK_NULL,
479 CLK_TOP_MAINPLL_D5
480};
481
482static const int nfiecc_parents[] = {
483 CLK_TOP_CLK_NULL,
484 CLK_TOP_NFI2X_PAD_SEL,
485 CLK_TOP_MAINPLL_D4,
486 CLK_TOP_CLK_NULL,
487 CLK_TOP_CSW_NFIECC_SEL,
488};
489
490static const struct mtk_composite top_muxes[] = {
491 /* CLK_MUX_SEL0 */
492 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
493 MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
494 MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
495 MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
496 MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
497 MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
498 MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
499 MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
500 MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
501 MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
502 MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
503 MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
504 MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
505 /* CLK_MUX_SEL1 */
506 MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
507 MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
508 MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
509 MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
510 MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
511 /* CLK_MUX_SEL8 */
512 MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
513 MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
514 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
515 MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
516 MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
517 MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
518 MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
519 MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
520 MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
521 MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
522 /* CLK_MUX_SEL9 */
523 MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
524 MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
525 MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
526 MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
527 MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
528 MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
529 MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
530 /* CLK_MUX_SEL13 */
531 MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
532 MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
533 MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
534 MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
535 MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
536 MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
537 MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
538 MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
539};
540
541static const struct mtk_gate_regs top0_cg_regs = {
542 .set_ofs = 0x50,
543 .clr_ofs = 0x80,
544 .sta_ofs = 0x20,
545};
546
547static const struct mtk_gate_regs top1_cg_regs = {
548 .set_ofs = 0x54,
549 .clr_ofs = 0x84,
550 .sta_ofs = 0x24,
551};
552
553static const struct mtk_gate_regs top2_cg_regs = {
554 .set_ofs = 0x6c,
555 .clr_ofs = 0x9c,
556 .sta_ofs = 0x3c,
557};
558
559static const struct mtk_gate_regs top3_cg_regs = {
560 .set_ofs = 0xa0,
561 .clr_ofs = 0xb0,
562 .sta_ofs = 0x70,
563};
564
565static const struct mtk_gate_regs top4_cg_regs = {
566 .set_ofs = 0xa4,
567 .clr_ofs = 0xb4,
568 .sta_ofs = 0x74,
569};
570
571static const struct mtk_gate_regs top5_cg_regs = {
572 .set_ofs = 0x44,
573 .clr_ofs = 0x44,
574 .sta_ofs = 0x44,
575};
576
577#define GATE_TOP0(_id, _parent, _shift) { \
578 .id = _id, \
579 .parent = _parent, \
580 .regs = &top0_cg_regs, \
581 .shift = _shift, \
582 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
583 }
584
585#define GATE_TOP1(_id, _parent, _shift) { \
586 .id = _id, \
587 .parent = _parent, \
588 .regs = &top1_cg_regs, \
589 .shift = _shift, \
590 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
591 }
592
593#define GATE_TOP2(_id, _parent, _shift) { \
594 .id = _id, \
595 .parent = _parent, \
596 .regs = &top2_cg_regs, \
597 .shift = _shift, \
598 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
599 }
600
601#define GATE_TOP2_I(_id, _parent, _shift) { \
602 .id = _id, \
603 .parent = _parent, \
604 .regs = &top2_cg_regs, \
605 .shift = _shift, \
606 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
607 }
608
609#define GATE_TOP3(_id, _parent, _shift) { \
610 .id = _id, \
611 .parent = _parent, \
612 .regs = &top3_cg_regs, \
613 .shift = _shift, \
614 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
615 }
616
617#define GATE_TOP4_I(_id, _parent, _shift) { \
618 .id = _id, \
619 .parent = _parent, \
620 .regs = &top4_cg_regs, \
621 .shift = _shift, \
622 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
623 }
624
625#define GATE_TOP5(_id, _parent, _shift) { \
626 .id = _id, \
627 .parent = _parent, \
628 .regs = &top5_cg_regs, \
629 .shift = _shift, \
630 .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
631 }
632
633static const struct mtk_gate top_clks[] = {
634 /* TOP0 */
635 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
636 GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),
637 GATE_TOP0(CLK_TOP_SPM_52M, CLK_TOP_SPM_52M_SEL, 3),
638 /* TOP1 */
639 GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
640 GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
641 GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
642 GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
643 GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
644 GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
645 GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
646 GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
647 GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
648 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
649 GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
650 GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
651 GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
652 GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
653 GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
654 GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
655 GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
656 GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
657 GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
658 GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
659 GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
660 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
661 GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
662 GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
663 GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
664 GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
665 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
666 GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
667 GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
668 GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
669 /* TOP2 */
670 GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
671 GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
672 GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
673 GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AHB_INFRA_SEL, 4),
674 GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
675 GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
676 GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
677 GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
678 GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
679 GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
680 GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
681 GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
682 GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
683 GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
684 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
685 GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
686 GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
687 GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
688 GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
689 GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
690 GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
691 GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
692 GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
693 GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
694 GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
695 GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
696 GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
697 /* TOP3 */
698 GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
699 GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
700 GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
701 GATE_TOP3(CLK_TOP_RG_AXI_MFG, CLK_TOP_AXI_MFG_IN_SEL, 6),
702 GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),
703 GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
704 GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
705 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
706 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
707 GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
708 GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
709 GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
710 GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
711 GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
712 GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
713 GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
714 /* TOP4 */
715 GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
716 GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
717 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
718 GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
719 GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
720 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
721 /* TOP5 */
722 GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
723 GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
724 GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
725 GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
726 GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
727 GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
728 GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
729 GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
730 GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
731};
732
733static const struct mtk_clk_tree mt8516_clk_tree = {
734 .xtal_rate = 26 * MHZ,
735 .xtal2_rate = 26 * MHZ,
736 .fdivs_offs = CLK_TOP_DMPLL,
737 .muxes_offs = CLK_TOP_UART0_SEL,
738 .plls = apmixed_plls,
739 .fclks = top_fixed_clks,
740 .fdivs = top_fixed_divs,
741 .muxes = top_muxes,
742};
743
744static int mt8516_apmixedsys_probe(struct udevice *dev)
745{
746 return mtk_common_clk_init(dev, &mt8516_clk_tree);
747}
748
749static int mt8516_topckgen_probe(struct udevice *dev)
750{
751 return mtk_common_clk_init(dev, &mt8516_clk_tree);
752}
753
754static int mt8516_topckgen_cg_probe(struct udevice *dev)
755{
756 return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
757}
758
759static const struct udevice_id mt8516_apmixed_compat[] = {
760 { .compatible = "mediatek,mt8516-apmixedsys", },
761 { }
762};
763
764static const struct udevice_id mt8516_topckgen_compat[] = {
765 { .compatible = "mediatek,mt8516-topckgen", },
766 { }
767};
768
769static const struct udevice_id mt8516_topckgen_cg_compat[] = {
770 { .compatible = "mediatek,mt8516-topckgen-cg", },
771 { }
772};
773
774U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
775 .name = "mt8516-apmixedsys",
776 .id = UCLASS_CLK,
777 .of_match = mt8516_apmixed_compat,
778 .probe = mt8516_apmixedsys_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]779 .priv_auto = sizeof(struct mtk_clk_priv),
Fabien Parent1fe5ad02019-03-24 16:46:36 +0100[diff] [blame]780 .ops = &mtk_clk_apmixedsys_ops,
781 .flags = DM_FLAG_PRE_RELOC,
782};
783
784U_BOOT_DRIVER(mtk_clk_topckgen) = {
785 .name = "mt8516-topckgen",
786 .id = UCLASS_CLK,
787 .of_match = mt8516_topckgen_compat,
788 .probe = mt8516_topckgen_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]789 .priv_auto = sizeof(struct mtk_clk_priv),
Fabien Parent1fe5ad02019-03-24 16:46:36 +0100[diff] [blame]790 .ops = &mtk_clk_topckgen_ops,
791 .flags = DM_FLAG_PRE_RELOC,
792};
793
794U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
795 .name = "mt8516-topckgen-cg",
796 .id = UCLASS_CLK,
797 .of_match = mt8516_topckgen_cg_compat,
798 .probe = mt8516_topckgen_cg_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]799 .priv_auto = sizeof(struct mtk_cg_priv),
Fabien Parent1fe5ad02019-03-24 16:46:36 +0100[diff] [blame]800 .ops = &mtk_clk_gate_ops,
801 .flags = DM_FLAG_PRE_RELOC,
802};