| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ROCKCHIP=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_ROCKCHIP_RK3288=y |
| Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 5 | CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y |
| Eddie Cai | 1e1a79f | 2017-01-18 11:03:54 +0800 | [diff] [blame] | 6 | CONFIG_TARGET_TINKER_RK3288=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 7 | CONFIG_SPL_STACK_R_ADDR=0x80000 |
| Eddie Cai | 1e1a79f | 2017-01-18 11:03:54 +0800 | [diff] [blame] | 8 | CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker" |
| Tom Rini | 256aa74 | 2017-06-19 09:47:40 -0400 | [diff] [blame] | 9 | CONFIG_DEBUG_UART=y |
| Tom Rini | b5bf562 | 2017-08-25 17:50:27 -0400 | [diff] [blame] | 10 | # CONFIG_ANDROID_BOOT_IMAGE is not set |
| Simon Glass | 4458d3b | 2016-10-17 20:12:35 -0600 | [diff] [blame] | 11 | CONFIG_SILENT_CONSOLE=y |
| Simon Glass | 9fd2a02 | 2016-10-17 20:12:37 -0600 | [diff] [blame] | 12 | CONFIG_CONSOLE_MUX=y |
| 13 | # CONFIG_DISPLAY_CPUINFO is not set |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 14 | CONFIG_SPL_STACK_R=y |
| 15 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 |
| Jonas Karlman | 269a37f | 2017-04-22 08:57:54 +0000 | [diff] [blame] | 16 | CONFIG_SPL_I2C_SUPPORT=y |
| Tom Rini | b5bf562 | 2017-08-25 17:50:27 -0400 | [diff] [blame] | 17 | CONFIG_FASTBOOT_FLASH=y |
| 18 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 19 | # CONFIG_CMD_IMLS is not set |
| Tom Rini | 78873cd | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 20 | CONFIG_CMD_GPIO=y |
| Patrick Delaunay | 7328709 | 2017-01-27 11:00:42 +0100 | [diff] [blame] | 21 | CONFIG_CMD_GPT=y |
| Tom Rini | 78873cd | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 22 | CONFIG_CMD_I2C=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 23 | CONFIG_CMD_MMC=y |
| 24 | CONFIG_CMD_SF=y |
| 25 | CONFIG_CMD_SPI=y |
| Eddie Cai | d1ba93e | 2017-03-07 12:47:07 +0800 | [diff] [blame] | 26 | CONFIG_CMD_USB=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 27 | # CONFIG_CMD_SETEXPR is not set |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 28 | CONFIG_CMD_CACHE=y |
| 29 | CONFIG_CMD_TIME=y |
| 30 | CONFIG_CMD_PMIC=y |
| 31 | CONFIG_CMD_REGULATOR=y |
| Patrick Delaunay | f7e0772 | 2017-01-27 11:00:37 +0100 | [diff] [blame] | 32 | # CONFIG_SPL_DOS_PARTITION is not set |
| Patrick Delaunay | 21d3bce | 2017-01-27 11:00:38 +0100 | [diff] [blame] | 33 | # CONFIG_SPL_ISO_PARTITION is not set |
| Patrick Delaunay | 8a4f2bd | 2017-01-27 11:00:41 +0100 | [diff] [blame] | 34 | # CONFIG_SPL_EFI_PARTITION is not set |
| Patrick Delaunay | 7328709 | 2017-01-27 11:00:42 +0100 | [diff] [blame] | 35 | CONFIG_SPL_PARTITION_UUIDS=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 36 | CONFIG_SPL_OF_CONTROL=y |
| 37 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| Tom Rini | 5b0b040 | 2017-08-28 07:16:32 -0400 | [diff] [blame] | 38 | CONFIG_ENV_IS_IN_MMC=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 39 | CONFIG_REGMAP=y |
| 40 | CONFIG_SPL_REGMAP=y |
| 41 | CONFIG_SYSCON=y |
| 42 | CONFIG_SPL_SYSCON=y |
| 43 | # CONFIG_SPL_SIMPLE_BUS is not set |
| 44 | CONFIG_CLK=y |
| 45 | CONFIG_SPL_CLK=y |
| 46 | CONFIG_ROCKCHIP_GPIO=y |
| 47 | CONFIG_SYS_I2C_ROCKCHIP=y |
| Jonas Karlman | 269a37f | 2017-04-22 08:57:54 +0000 | [diff] [blame] | 48 | CONFIG_MISC=y |
| 49 | CONFIG_I2C_EEPROM=y |
| Masahiro Yamada | 7942e91 | 2017-01-10 13:32:04 +0900 | [diff] [blame] | 50 | CONFIG_MMC_DW=y |
| Masahiro Yamada | dc607f8 | 2017-01-10 13:32:03 +0900 | [diff] [blame] | 51 | CONFIG_MMC_DW_ROCKCHIP=y |
| Jacob Chen | 5c3166d | 2017-02-23 14:20:17 +0800 | [diff] [blame] | 52 | CONFIG_DM_ETH=y |
| Jacob Chen | 5c3166d | 2017-02-23 14:20:17 +0800 | [diff] [blame] | 53 | CONFIG_ETH_DESIGNWARE=y |
| 54 | CONFIG_GMAC_ROCKCHIP=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 55 | CONFIG_PINCTRL=y |
| 56 | CONFIG_SPL_PINCTRL=y |
| 57 | # CONFIG_SPL_PINCTRL_FULL is not set |
| Philipp Tomsich | a1dcf3c | 2017-04-19 16:46:37 +0200 | [diff] [blame] | 58 | CONFIG_PINCTRL_ROCKCHIP_RK3288=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 59 | CONFIG_DM_PMIC=y |
| Jacob Chen | 614704b | 2017-05-02 14:54:52 +0800 | [diff] [blame] | 60 | CONFIG_PMIC_RK8XX=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 61 | CONFIG_DM_REGULATOR_FIXED=y |
| Jacob Chen | 614704b | 2017-05-02 14:54:52 +0800 | [diff] [blame] | 62 | CONFIG_REGULATOR_RK8XX=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 63 | CONFIG_PWM_ROCKCHIP=y |
| 64 | CONFIG_RAM=y |
| 65 | CONFIG_SPL_RAM=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 66 | CONFIG_DEBUG_UART_BASE=0xff690000 |
| 67 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| 68 | CONFIG_DEBUG_UART_SHIFT=2 |
| 69 | CONFIG_SYS_NS16550=y |
| Tom Rini | afea41d | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 70 | CONFIG_SYSRESET=y |
| Eddie Cai | d1ba93e | 2017-03-07 12:47:07 +0800 | [diff] [blame] | 71 | CONFIG_USB=y |
| Philipp Tomsich | 5498381 | 2017-07-03 18:30:06 +0200 | [diff] [blame] | 72 | CONFIG_USB_DWC2=y |
| Eddie Cai | d1ba93e | 2017-03-07 12:47:07 +0800 | [diff] [blame] | 73 | CONFIG_USB_STORAGE=y |
| Tom Rini | 504997e | 2017-08-25 17:50:26 -0400 | [diff] [blame] | 74 | CONFIG_USB_GADGET=y |
| 75 | CONFIG_USB_GADGET_DWC2_OTG=y |
| 76 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 77 | CONFIG_G_DNL_MANUFACTURER="Rockchip" |
| 78 | CONFIG_G_DNL_VENDOR_NUM=0x2207 |
| 79 | CONFIG_G_DNL_PRODUCT_NUM=0x320a |
| Chris Packham | 547cf41 | 2017-08-28 20:50:45 +1200 | [diff] [blame^] | 80 | CONFIG_USB_HOST_ETHER=y |
| Xu Ziyuan | 535b3dc | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 81 | CONFIG_USE_TINY_PRINTF=y |
| 82 | CONFIG_CMD_DHRYSTONE=y |
| 83 | CONFIG_ERRNO_STR=y |