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git01.mediatek.com / filogic / uboot / b096740cc7c973ddb2c0147a2a5bf7b7a8729d02 / . / drivers / mmc / octeontx_hsmmc.h
blob: 9849121f1749242e0ab99672de091dae3464cfea [file] [log] [blame]
Suneel Garapati40e61332019-10-19 18:03:01 -0700[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2019 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7#ifndef __OCTEONTX_HSMMC_H__
8#define __OCTEONTX_HSMMC_H__
9#include <asm/gpio.h>
10
11/** Name of our driver */
12#define OCTEONTX_MMC_DRIVER_NAME "octeontx-hsmmc"
13
14/** Maximum supported MMC slots */
15#define OCTEONTX_MAX_MMC_SLOT 3
16
17#define POWER_ON_TIME 40 /** See SD 4.1 spec figure 6-5 */
18
19/**
20 * Timeout used when waiting for commands to complete. We need to keep this
21 * above the hardware watchdog timeout which is usually limited to 1000ms
22 */
23#define WATCHDOG_COUNT (1100) /* in msecs */
24
25/**
26 * Long timeout for commands which might take a while to complete.
27 */
28#define MMC_TIMEOUT_LONG 1000
29
30/**
31 * Short timeout used for most commands in msecs
32 */
33#define MMC_TIMEOUT_SHORT 20
34
Suneel Garapati40e61332019-10-19 18:03:01 -0700[diff] [blame]35#define MAX_NO_OF_TAPS 64
36
37#define EXT_CSD_POWER_CLASS 187 /* R/W */
38
39/* default HS400 tuning block number */
40#define DEFAULT_HS400_TUNING_BLOCK 1
41
42struct octeontx_mmc_host;
43
44/** MMC/SD slot data structure */
45struct octeontx_mmc_slot {
46 struct mmc mmc;
47 struct mmc_config cfg;
48 struct octeontx_mmc_host *host;
49 struct udevice *dev;
50 void *base_addr; /** Same as host base_addr */
51 u64 clock;
52 int bus_id; /** slot number */
53 uint bus_width;
54 uint max_width;
55 int hs200_tap_adj;
56 int hs400_tap_adj;
57 int hs400_tuning_block;
58 struct gpio_desc cd_gpio;
59 struct gpio_desc wp_gpio;
60 struct gpio_desc power_gpio;
61 enum bus_mode mode;
62 union mio_emm_switch cached_switch;
63 union mio_emm_switch want_switch;
64 union mio_emm_rca cached_rca;
65 union mio_emm_timing taps; /* otx2: MIO_EMM_TIMING */
66 union mio_emm_timing hs200_taps;
67 union mio_emm_timing hs400_taps;
68 /* These are used to see if our tuning is still valid or not */
69 enum bus_mode last_mode;
70 u32 last_clock;
71 u32 block_len;
72 u32 block_count;
73 int cmd_clk_skew;
74 int dat_clk_skew;
75 uint cmd_cnt; /* otx: sample cmd in delay */
76 uint dat_cnt; /* otx: sample data in delay */
77 uint drive; /* Current drive */
78 uint slew; /* clock skew */
79 uint cmd_out_hs200_delay;
80 uint data_out_hs200_delay;
81 uint cmd_out_hs400_delay;
82 uint data_out_hs400_delay;
83 uint clk_period;
84 bool valid:1;
85 bool is_acmd:1;
86 bool tuned:1;
87 bool hs200_tuned:1;
88 bool hs400_tuned:1;
89 bool is_1_8v:1;
90 bool is_3_3v:1;
91 bool is_ddr:1;
92 bool is_asim:1;
93 bool is_emul:1;
94 bool cd_inverted:1;
95 bool wp_inverted:1;
96 bool disable_ddr:1;
97 bool non_removable:1;
98};
99
100struct octeontx_mmc_cr_mods {
101 u8 ctype_xor;
102 u8 rtype_xor;
103};
104
105struct octeontx_mmc_cr {
106 u8 c;
107 u8 r;
108};
109
110struct octeontx_sd_mods {
111 struct octeontx_mmc_cr mmc;
112 struct octeontx_mmc_cr sd;
113 struct octeontx_mmc_cr sdacmd;
114};
115
116/** Host controller data structure */
117struct octeontx_mmc_host {
118 struct udevice *dev;
119 void *base_addr;
120 struct octeontx_mmc_slot slots[OCTEONTX_MAX_MMC_SLOT + 1];
121 pci_dev_t pdev;
122 u64 sys_freq;
123 union mio_emm_cfg emm_cfg;
124 u64 timing_taps;
125 struct mmc *last_mmc; /** Last mmc used */
126 ofnode node;
127 int cur_slotid;
128 int last_slotid;
129 int max_width;
130 uint per_tap_delay;
131 uint num_slots;
132 uint dma_wait_delay; /* Delay before polling DMA in usecs */
133 bool initialized:1;
134 bool timing_calibrated:1;
135 bool is_asim:1;
136 bool is_emul:1;
137 bool calibrate_glitch:1;
138 bool cond_clock_glitch:1;
139 bool tap_requires_noclk:1;
140 bool hs400_skew_needed:1;
141};
142
143/*
144 * NOTE: This was copied from the Linux kernel.
145 *
146 * MMC status in R1, for native mode (SPI bits are different)
147 * Type
148 * e:error bit
149 * s:status bit
150 * r:detected and set for the actual command response
151 * x:detected and set during command execution. the host must poll
152 * the card by sending status command in order to read these bits.
153 * Clear condition
154 * a:according to the card state
155 * b:always related to the previous command. Reception of
156 * a valid command will clear it (with a delay of one command)
157 * c:clear by read
158 */
159#define R1_OUT_OF_RANGE BIT(31) /* er, c */
160#define R1_ADDRESS_ERROR BIT(30) /* erx, c */
161#define R1_BLOCK_LEN_ERROR BIT(29) /* er, c */
162#define R1_ERASE_SEQ_ERROR BIT(28) /* er, c */
163#define R1_ERASE_PARAM BIT(27) /* ex, c */
164#define R1_WP_VIOLATION BIT(26) /* erx, c */
165#define R1_CARD_IS_LOCKED BIT(25) /* sx, a */
166#define R1_LOCK_UNLOCK_FAILED BIT(24) /* erx, c */
167#define R1_COM_CRC_ERROR BIT(23) /* er, b */
168/*#define R1_ILLEGAL_COMMAND BIT(22)*/ /* er, b */
169#define R1_CARD_ECC_FAILED BIT(21) /* ex, c */
170#define R1_CC_ERROR BIT(20) /* erx, c */
171#define R1_ERROR BIT(19) /* erx, c */
172#define R1_UNDERRUN BIT(18) /* ex, c */
173#define R1_OVERRUN BIT(17) /* ex, c */
174#define R1_CID_CSD_OVERWRITE BIT(16) /* erx, c, CID/CSD overwrite */
175#define R1_WP_ERASE_SKIP BIT(15) /* sx, c */
176#define R1_CARD_ECC_DISABLED BIT(14) /* sx, a */
177#define R1_ERASE_RESET BIT(13) /* sr, c */
178#define R1_STATUS(x) ((x) & 0xFFFFE000)
179#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */
180#define R1_READY_FOR_DATA BIT(8) /* sx, a */
181#define R1_SWITCH_ERROR BIT(7) /* sx, c */
182
183#define R1_BLOCK_READ_MASK R1_OUT_OF_RANGE | \
184 R1_ADDRESS_ERROR | \
185 R1_BLOCK_LEN_ERROR | \
186 R1_CARD_IS_LOCKED | \
187 R1_COM_CRC_ERROR | \
188 R1_ILLEGAL_COMMAND | \
189 R1_CARD_ECC_FAILED | \
190 R1_CC_ERROR | \
191 R1_ERROR
192#define R1_BLOCK_WRITE_MASK R1_OUT_OF_RANGE | \
193 R1_ADDRESS_ERROR | \
194 R1_BLOCK_LEN_ERROR | \
195 R1_WP_VIOLATION | \
196 R1_CARD_IS_LOCKED | \
197 R1_COM_CRC_ERROR | \
198 R1_ILLEGAL_COMMAND | \
199 R1_CARD_ECC_FAILED | \
200 R1_CC_ERROR | \
201 R1_ERROR | \
202 R1_UNDERRUN | \
203 R1_OVERRUN
204
205#endif /* __OCTEONTX_HSMMC_H__ */