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git01.mediatek.com / filogic / uboot / 55152230115040710211692ab25c0eb89d3a7c11 / . / arch / arm / mach-rockchip / rk3588 / rk3588.c
blob: 2ee1db47671feeffe5b1fa6f9f478b2d4a3bab52 [file] [log] [blame]
Jagan Teki8967dea2023-01-30 20:27:45 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd
4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
5 */
6
7#include <common.h>
8#include <spl.h>
9#include <asm/armv8/mmu.h>
10#include <asm/io.h>
11#include <asm/arch-rockchip/hardware.h>
12#include <asm/arch-rockchip/ioc_rk3588.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16#define FIREWALL_DDR_BASE 0xfe030000
17#define FW_DDR_MST5_REG 0x54
18#define FW_DDR_MST13_REG 0x74
19#define FW_DDR_MST21_REG 0x94
20#define FW_DDR_MST26_REG 0xa8
21#define FW_DDR_MST27_REG 0xac
22#define FIREWALL_SYSMEM_BASE 0xfe038000
23#define FW_SYSM_MST5_REG 0x54
24#define FW_SYSM_MST13_REG 0x74
25#define FW_SYSM_MST21_REG 0x94
26#define FW_SYSM_MST26_REG 0xa8
27#define FW_SYSM_MST27_REG 0xac
28
29#define PMU1_IOC_BASE 0xfd5f0000
30#define PMU2_IOC_BASE 0xfd5f4000
31
32#define BUS_IOC_BASE 0xfd5f8000
33#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
34#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
35#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
36#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
37#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
38
39static struct mm_region rk3588_mem_map[] = {
40 {
41 .virt = 0x0UL,
42 .phys = 0x0UL,
43 .size = 0xf0000000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45 PTE_BLOCK_INNER_SHARE
46 }, {
47 .virt = 0xf0000000UL,
48 .phys = 0xf0000000UL,
49 .size = 0x10000000UL,
50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51 PTE_BLOCK_NON_SHARE |
52 PTE_BLOCK_PXN | PTE_BLOCK_UXN
53 }, {
54 .virt = 0x900000000,
55 .phys = 0x900000000,
56 .size = 0x150000000,
57 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
58 PTE_BLOCK_NON_SHARE |
59 PTE_BLOCK_PXN | PTE_BLOCK_UXN
60 }, {
61 /* List terminator */
62 0,
63 }
64};
65
66struct mm_region *mem_map = rk3588_mem_map;
67
68/* GPIO0B_IOMUX_SEL_H */
69enum {
70 GPIO0B5_SHIFT = 4,
71 GPIO0B5_MASK = GENMASK(7, 4),
72 GPIO0B5_REFER = 8,
73 GPIO0B5_UART2_TX_M0 = 10,
74
75 GPIO0B6_SHIFT = 8,
76 GPIO0B6_MASK = GENMASK(11, 8),
77 GPIO0B6_REFER = 8,
78 GPIO0B6_UART2_RX_M0 = 10,
79};
80
81void board_debug_uart_init(void)
82{
83 __maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
84 static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
85
86 /* Refer to BUS_IOC */
87 rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
88 GPIO0B6_MASK | GPIO0B5_MASK,
89 GPIO0B6_REFER << GPIO0B6_SHIFT |
90 GPIO0B5_REFER << GPIO0B5_SHIFT);
91
92 /* UART2_M0 Switch iomux */
93 rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
94 GPIO0B6_MASK | GPIO0B5_MASK,
95 GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
96 GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
97}
98
99#ifdef CONFIG_SPL_BUILD
100void rockchip_stimer_init(void)
101{
102 /* If Timer already enabled, don't re-init it */
103 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
104
105 if (reg & 0x1)
106 return;
107
108 asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
109 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
110 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
111 writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
112}
113#endif
114
115#ifndef CONFIG_TPL_BUILD
116int arch_cpu_init(void)
117{
118#ifdef CONFIG_SPL_BUILD
119 int secure_reg;
120
121 /* Set the SDMMC eMMC crypto_ns FSPI access secure area */
122 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
123 secure_reg &= 0xffff;
124 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
125 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
126 secure_reg &= 0xffff;
127 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
128 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
129 secure_reg &= 0xffff;
130 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
131 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
132 secure_reg &= 0xffff;
133 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
134 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
135 secure_reg &= 0xffff0000;
136 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
137
138 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
139 secure_reg &= 0xffff;
140 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
141 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
142 secure_reg &= 0xffff;
143 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
144 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
145 secure_reg &= 0xffff;
146 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
147 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
148 secure_reg &= 0xffff;
149 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
150 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
151 secure_reg &= 0xffff0000;
152 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
153#endif
154
155 return 0;
156}
157#endif