blob: 15256302b86b2b6c72ea405a909ae5ca3a2d4037 [file] [log] [blame]
Daniel Gollef8c29bf2023-04-11 17:19:46 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7986.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "BananaPi BPi-R3";
15 compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb";
16
17 chosen {
18 stdout-path = &uart0;
19 tick-timer = &timer0;
20 };
21
developer87bf1bc2023-07-19 17:15:41 +080022 memory@40000000 {
23 device_type = "memory";
24 reg = <0x40000000 0x80000000>;
25 };
26
Daniel Gollef8c29bf2023-04-11 17:19:46 +020027 reg_3p3v: regulator-3p3v {
28 compatible = "regulator-fixed";
29 regulator-name = "fixed-3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 regulator-boot-on;
33 regulator-always-on;
34 };
35
36 keys {
37 compatible = "gpio-keys";
38
39 factory {
40 label = "reset";
41 gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
42 };
43
44 wps {
45 label = "wps";
46 gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
47 };
48 };
49
50 leds {
51 compatible = "gpio-leds";
52
53 led_status_green: green {
54 label = "green:status";
55 gpios = <&gpio 69 GPIO_ACTIVE_HIGH>;
56 };
57
58 led_status_blue: blue {
59 label = "blue:status";
60 gpios = <&gpio 86 GPIO_ACTIVE_HIGH>;
61 };
62 };
63
64};
65
66&uart0 {
67 status = "okay";
68};
69
70&uart1 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&uart1_pins>;
73 status = "disabled";
74};
75
76&eth {
77 status = "okay";
78 mediatek,gmac-id = <0>;
79 phy-mode = "sgmii";
80 mediatek,switch = "mt7531";
81 reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
82
83 fixed-link {
84 speed = <1000>;
85 full-duplex;
86 };
87};
88
89&pinctrl {
90 spic_pins: spi1-pins-func-1 {
91 mux {
92 function = "spi";
93 groups = "spi1_2";
94 };
95 };
96
97 uart1_pins: spi1-pins-func-3 {
98 mux {
99 function = "uart";
100 groups = "uart1_2";
101 };
102 };
103
104 pwm_pins: pwm0-pins-func-1 {
105 mux {
106 function = "pwm";
107 groups = "pwm0";
108 };
109 };
110
111 mmc0_pins_default: mmc0default {
112 mux {
113 function = "flash";
114 groups = "emmc_51";
115 };
116
117 conf-cmd-dat {
118 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
119 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
120 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
121 input-enable;
122 drive-strength = <MTK_DRIVE_4mA>;
123 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
124 };
125
126 conf-clk {
127 pins = "EMMC_CK";
128 drive-strength = <MTK_DRIVE_6mA>;
129 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
130 };
131
132 conf-dsl {
133 pins = "EMMC_DSL";
134 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
135 };
136
137 conf-rst {
138 pins = "EMMC_RSTB";
139 drive-strength = <MTK_DRIVE_4mA>;
140 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
141 };
142 };
143
144 spi_flash_pins: spi0-pins-func-1 {
145 mux {
146 function = "flash";
147 groups = "spi0", "spi0_wp_hold";
148 };
149
150 conf-pu {
151 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
152 drive-strength = <MTK_DRIVE_8mA>;
153 bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
154 };
155
156 conf-pd {
157 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
158 drive-strength = <MTK_DRIVE_8mA>;
159 bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
160 };
161 };
162};
163
164&pwm {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pwm_pins>;
167 status = "okay";
168};
169
170&spi0 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&spi_flash_pins>;
175 status = "okay";
176 must_tx;
177 enhance_timing;
178 dma_ext;
179 ipm_design;
180 support_quad;
181 tick_dly = <1>;
182 sample_sel = <0>;
183
184 spi_nor@0 {
185 compatible = "jedec,spi-nor";
186 reg = <0>;
187 spi-max-frequency = <52000000>;
188
189 partitions {
190 compatible = "fixed-partitions";
191 #address-cells = <1>;
192 #size-cells = <1>;
193
194 partition@0 {
195 label = "bl2";
196 reg = <0x0 0x40000>;
197 };
198
199 partition@40000 {
200 label = "u-boot-env";
201 reg = <0x40000 0x40000>;
202 };
203
204 partition@80000 {
205 label = "reserved";
206 reg = <0x80000 0x80000>;
207 };
208
209 partition@100000 {
210 label = "fip";
211 reg = <0x100000 0x80000>;
212 };
213
214 partition@180000 {
215 label = "recovery";
216 reg = <0x180000 0xa80000>;
217 };
218
219 partition@c00000 {
220 label = "fit";
221 reg = <0xc00000 0x1400000>;
222 };
223 };
224 };
225
226 spi_nand@1 {
227 compatible = "spi-nand";
228 reg = <1>;
229 spi-max-frequency = <52000000>;
230
231 partitions {
232 compatible = "fixed-partitions";
233 #address-cells = <1>;
234 #size-cells = <1>;
235
236 partition@0 {
237 label = "bl2";
238 reg = <0x0 0x80000>;
239 };
240
241 partition@80000 {
242 label = "factory";
243 reg = <0x80000 0x300000>;
244 };
245
246 partition@380000 {
247 label = "fip";
248 reg = <0x380000 0x200000>;
249 };
250
251 partition@580000 {
252 label = "ubi";
253 reg = <0x580000 0x7a80000>;
254 };
255 };
256 };
257};
258
259&watchdog {
260 status = "disabled";
261};
262
263&mmc0 {
264 pinctrl-names = "default";
265 pinctrl-0 = <&mmc0_pins_default>;
266 bus-width = <4>;
267 max-frequency = <52000000>;
268 cap-sd-highspeed;
269 r_smpl = <1>;
270 vmmc-supply = <&reg_3p3v>;
271 vqmmc-supply = <&reg_3p3v>;
272 status = "okay";
273};