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git01.mediatek.com / filogic / uboot / 7bf27253da95348788b8d9d723e4ac5fff77b945 / . / arch / arm / cpu / armv8 / exceptions.S
blob: 1a78a5d1dcc7e577fe23edccc926d6878fbe9fe2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
David Feng85fd5f12013-12-14 11:47:35 +0800[diff] [blame]2/*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
David Feng85fd5f12013-12-14 11:47:35 +0800[diff] [blame]5 */
6
7#include <asm-offsets.h>
8#include <config.h>
David Feng85fd5f12013-12-14 11:47:35 +0800[diff] [blame]9#include <asm/ptrace.h>
10#include <asm/macro.h>
11#include <linux/linkage.h>
12
13/*
Andre Przywara143362c2017-11-27 00:47:09 +0000[diff] [blame]14 * Exception vectors.
15 */
16 .align 11
17 .globl vectors
18vectors:
19 .align 7 /* Current EL Synchronous Thread */
20 stp x29, x30, [sp, #-16]!
21 bl _exception_entry
22 bl do_bad_sync
23 b exception_exit
24
25 .align 7 /* Current EL IRQ Thread */
26 stp x29, x30, [sp, #-16]!
27 bl _exception_entry
28 bl do_bad_irq
29 b exception_exit
30
31 .align 7 /* Current EL FIQ Thread */
32 stp x29, x30, [sp, #-16]!
33 bl _exception_entry
34 bl do_bad_fiq
35 b exception_exit
36
37 .align 7 /* Current EL Error Thread */
38 stp x29, x30, [sp, #-16]!
39 bl _exception_entry
40 bl do_bad_error
41 b exception_exit
42
43 .align 7 /* Current EL Synchronous Handler */
44 stp x29, x30, [sp, #-16]!
45 bl _exception_entry
46 bl do_sync
47 b exception_exit
48
49 .align 7 /* Current EL IRQ Handler */
50 stp x29, x30, [sp, #-16]!
51 bl _exception_entry
52 bl do_irq
53 b exception_exit
54
55 .align 7 /* Current EL FIQ Handler */
56 stp x29, x30, [sp, #-16]!
57 bl _exception_entry
58 bl do_fiq
59 b exception_exit
60
61 .align 7 /* Current EL Error Handler */
62 stp x29, x30, [sp, #-16]!
63 bl _exception_entry
64 bl do_error
65 b exception_exit
66
67/*
David Feng85fd5f12013-12-14 11:47:35 +0800[diff] [blame]68 * Enter Exception.
69 * This will save the processor state that is ELR/X0~X30
70 * to the stack frame.
71 */
Andre Przywara143362c2017-11-27 00:47:09 +0000[diff] [blame]72_exception_entry:
David Feng85fd5f12013-12-14 11:47:35 +0800[diff] [blame]73 stp x27, x28, [sp, #-16]!
74 stp x25, x26, [sp, #-16]!
75 stp x23, x24, [sp, #-16]!
76 stp x21, x22, [sp, #-16]!
77 stp x19, x20, [sp, #-16]!
78 stp x17, x18, [sp, #-16]!
79 stp x15, x16, [sp, #-16]!
80 stp x13, x14, [sp, #-16]!
81 stp x11, x12, [sp, #-16]!
82 stp x9, x10, [sp, #-16]!
83 stp x7, x8, [sp, #-16]!
84 stp x5, x6, [sp, #-16]!
85 stp x3, x4, [sp, #-16]!
86 stp x1, x2, [sp, #-16]!
87
88 /* Could be running at EL3/EL2/EL1 */
89 switch_el x11, 3f, 2f, 1f
903: mrs x1, esr_el3
91 mrs x2, elr_el3
92 b 0f
932: mrs x1, esr_el2
94 mrs x2, elr_el2
95 b 0f
961: mrs x1, esr_el1
97 mrs x2, elr_el1
980:
99 stp x2, x0, [sp, #-16]!
100 mov x0, sp
Andre Przywara143362c2017-11-27 00:47:09 +0000[diff] [blame]101 ret
David Feng85fd5f12013-12-14 11:47:35 +0800[diff] [blame]102
Alexander Graf99adbd92016-03-04 01:10:05 +0100[diff] [blame]103
104exception_exit:
105 ldp x2, x0, [sp],#16
106 switch_el x11, 3f, 2f, 1f
1073: msr elr_el3, x2
108 b 0f
1092: msr elr_el2, x2
110 b 0f
1111: msr elr_el1, x2
1120:
113 ldp x1, x2, [sp],#16
114 ldp x3, x4, [sp],#16
115 ldp x5, x6, [sp],#16
116 ldp x7, x8, [sp],#16
117 ldp x9, x10, [sp],#16
118 ldp x11, x12, [sp],#16
119 ldp x13, x14, [sp],#16
120 ldp x15, x16, [sp],#16
121 ldp x17, x18, [sp],#16
122 ldp x19, x20, [sp],#16
123 ldp x21, x22, [sp],#16
124 ldp x23, x24, [sp],#16
125 ldp x25, x26, [sp],#16
126 ldp x27, x28, [sp],#16
127 ldp x29, x30, [sp],#16
128 eret