| Svyatoslav Ryhel | fcb1d91 | 2023-06-30 10:29:05 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /dts-v1/; |
| 3 | |
| 4 | #include "tegra30-lg-x3.dtsi" |
| 5 | |
| 6 | / { |
| 7 | model = "LG Optimus Vu"; |
| 8 | compatible = "lge,p895", "nvidia,tegra30"; |
| 9 | |
| 10 | gpio-keys { |
| 11 | key-volume-up { |
| 12 | label = "Volume Up"; |
| 13 | gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>; |
| 14 | linux,code = <KEY_UP>; |
| 15 | }; |
| 16 | }; |
| 17 | |
| Svyatoslav Ryhel | aef10d8 | 2023-11-27 19:08:32 +0200 | [diff] [blame] | 18 | pinmux@70000868 { |
| 19 | state_default: pinmux { |
| 20 | /* GNSS UART-B pinmux */ |
| 21 | uartb_cts_rxd { |
| 22 | nvidia,pins = "uart2_cts_n_pj5", |
| 23 | "uart2_rxd_pc3"; |
| 24 | nvidia,function = "uartb"; |
| 25 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 26 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 27 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 28 | }; |
| 29 | uartb_rts_txd { |
| 30 | nvidia,pins = "uart2_rts_n_pj6", |
| 31 | "uart2_txd_pc2"; |
| 32 | nvidia,function = "uartb"; |
| 33 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 34 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 35 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 36 | }; |
| 37 | gps_reset { |
| 38 | nvidia,pins = "spdif_out_pk5"; |
| 39 | nvidia,function = "spdif"; |
| 40 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 41 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 42 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 43 | }; |
| 44 | |
| 45 | /* GPIO keys pinmux */ |
| 46 | volume_up { |
| 47 | nvidia,pins = "gmi_cs7_n_pi6"; |
| 48 | nvidia,function = "gmi"; |
| 49 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 50 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 51 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 52 | }; |
| 53 | memo_key { |
| 54 | nvidia,pins = "sdmmc3_dat1_pb6"; |
| 55 | nvidia,function = "rsvd1"; |
| 56 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 57 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 58 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 59 | }; |
| 60 | |
| 61 | /* Sensors pinmux */ |
| 62 | current_alert_irq { |
| 63 | nvidia,pins = "spi1_cs0_n_px6"; |
| 64 | nvidia,function = "gmi"; |
| 65 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 66 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 67 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 68 | }; |
| 69 | |
| 70 | /* Panel pinmux */ |
| 71 | panel_vdd { |
| 72 | nvidia,pins = "pbb0"; |
| 73 | nvidia,function = "rsvd2"; |
| 74 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 75 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 76 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 77 | }; |
| 78 | |
| 79 | /* AUDIO pinmux */ |
| 80 | sub_mic_ldo { |
| 81 | nvidia,pins = "gmi_dqs_pi2"; |
| 82 | nvidia,function = "gmi"; |
| 83 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 84 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 85 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 86 | }; |
| 87 | |
| 88 | /* Modem pinmux */ |
| 89 | usim_detect { |
| 90 | nvidia,pins = "clk2_out_pw5"; |
| 91 | nvidia,function = "rsvd2"; |
| 92 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 93 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 94 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 95 | }; |
| 96 | |
| 97 | /* GPIO power/drive control */ |
| 98 | drive_sdmmc4 { |
| 99 | nvidia,pins = "drive_gma", |
| 100 | "drive_gmb", |
| 101 | "drive_gmc", |
| 102 | "drive_gmd"; |
| 103 | nvidia,pull-down-strength = <9>; |
| 104 | nvidia,pull-up-strength = <9>; |
| 105 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 106 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 107 | }; |
| 108 | }; |
| 109 | }; |
| 110 | |
| Svyatoslav Ryhel | fcb1d91 | 2023-06-30 10:29:05 +0300 | [diff] [blame] | 111 | panel: panel { |
| 112 | compatible = "hitachi,tx13d100vm0eaa"; |
| 113 | |
| 114 | reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
| 115 | |
| 116 | renesas,gamma = <3>; |
| 117 | renesas,inversion; |
| 118 | renesas,contrast; |
| 119 | |
| 120 | vcc-supply = <&vcc_3v0_lcd>; |
| 121 | iovcc-supply = <&iovcc_1v8_lcd>; |
| 122 | |
| 123 | backlight = <&backlight>; |
| 124 | }; |
| 125 | |
| 126 | vcc_3v0_lcd: regulator-lcd { |
| 127 | compatible = "regulator-fixed"; |
| 128 | regulator-name = "vcc_3v0_lcd"; |
| 129 | regulator-min-microvolt = <3000000>; |
| 130 | regulator-max-microvolt = <3000000>; |
| 131 | gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>; |
| 132 | enable-active-high; |
| 133 | }; |
| 134 | |
| 135 | iovcc_1v8_lcd: regulator-lcdvio { |
| 136 | compatible = "regulator-fixed"; |
| 137 | regulator-name = "iovcc_1v8_lcd"; |
| 138 | regulator-min-microvolt = <1800000>; |
| 139 | regulator-max-microvolt = <1800000>; |
| 140 | gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; |
| 141 | enable-active-high; |
| 142 | }; |
| 143 | }; |