blob: bc047d4b44309d045bddcbe9dbcb61a9a8d581b7 [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
4
5/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&gic>;
9
10 /* external reference clock */
11 clk_refclk: clk-refclk {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <25000000>;
15 clock-output-names = "refclk";
16 };
17
18 ahb {
19 rstc: reset-controller@f0801000 {
20 compatible = "nuvoton,npcm845-reset", "syscon",
21 "simple-mfd";
22 reg = <0x0 0xf0801000 0x0 0xC4>;
Jim Liuae378012024-01-24 09:54:51 +080023 #reset-cells = <2>;
Jim Liu147c0002022-09-27 16:45:15 +080024 };
25
26 clk: clock-controller@f0801000 {
27 compatible = "nuvoton,npcm845-clk", "syscon";
28 #clock-cells = <1>;
29 clock-controller;
30 reg = <0x0 0xf0801000 0x0 0x1000>;
31 clock-names = "refclk";
32 clocks = <&clk_refclk>;
33 };
34
Jim Liu2e4fb4e2023-01-17 16:59:21 +080035 gmac0: eth@f0802000 {
36 device_type = "network";
37 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
38 reg = <0x0 0xf0802000 0x0 0x2000>,
39 <0x0 0xf0780000 0x0 0x200>;
40 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
41 interrupt-names = "macirq";
42 clocks = <&clk NPCM8XX_CLK_AHB>;
43 clock-names = "stmmaceth";
44 pinctrl-names = "default";
45 pinctrl-0 = <&rg1mdio_pins>;
Jim Liuae378012024-01-24 09:54:51 +080046 resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC1>;
Jim Liu2e4fb4e2023-01-17 16:59:21 +080047 status = "disabled";
48 };
49
50 gmac1: eth@f0804000 {
51 device_type = "network";
52 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
53 reg = <0x0 0xf0804000 0x0 0x2000>;
54 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
55 interrupt-names = "macirq";
56 clocks = <&clk NPCM8XX_CLK_AHB>;
57 clock-names = "stmmaceth";
58 pinctrl-names = "default";
59 pinctrl-0 = <&rg2_pins
60 &rg2mdio_pins>;
Jim Liuae378012024-01-24 09:54:51 +080061 resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC2>;
Jim Liu2e4fb4e2023-01-17 16:59:21 +080062 status = "disabled";
63 };
64
65 gmac2: eth@f0806000 {
66 device_type = "network";
67 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
68 reg = <0x0 0xf0806000 0x0 0x2000>;
69 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-names = "macirq";
71 clocks = <&clk NPCM8XX_CLK_AHB>;
72 clock-names = "stmmaceth";
73 pinctrl-names = "default";
74 pinctrl-0 = <&r1_pins
75 &r1err_pins
76 &r1md_pins>;
Jim Liuae378012024-01-24 09:54:51 +080077 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC3>;
Jim Liu2e4fb4e2023-01-17 16:59:21 +080078 status = "disabled";
79 };
80
81 gmac3: eth@f0808000 {
82 device_type = "network";
83 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
84 reg = <0x0 0xf0808000 0x0 0x2000>;
85 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-names = "macirq";
87 clocks = <&clk NPCM8XX_CLK_AHB>;
88 clock-names = "stmmaceth";
89 pinctrl-names = "default";
90 pinctrl-0 = <&r2_pins
91 &r2err_pins
92 &r2md_pins>;
Jim Liuae378012024-01-24 09:54:51 +080093 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC4>;
Jim Liu2e4fb4e2023-01-17 16:59:21 +080094 status = "disabled";
95 };
96
Jim Liu89b26542022-11-28 10:32:44 +080097 ehci1: usb@f0828100 {
98 compatible = "nuvoton,npcm845-ehci";
99 reg = <0x0 0xf0828100 0x0 0x1000>;
100 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
Jim Liuae378012024-01-24 09:54:51 +0800101 resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>;
Jim Liu89b26542022-11-28 10:32:44 +0800102 status = "disabled";
103 };
104
105 ehci2: usb@f082a100 {
106 compatible = "nuvoton,npcm845-ehci";
107 reg = <0x0 0xf082a100 0x0 0x1000>;
108 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
Jim Liuae378012024-01-24 09:54:51 +0800109 resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>;
Jim Liu89b26542022-11-28 10:32:44 +0800110 status = "disabled";
111 };
112
113 ohci1: usb@f0829000 {
114 compatible = "nuvoton,npcm845-ohci";
115 reg = <0x0 0xF0829000 0x0 0x1000>;
Jim Liuae378012024-01-24 09:54:51 +0800116 resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>;
Jim Liu89b26542022-11-28 10:32:44 +0800117 status = "disabled";
118 };
119
120 ohci2: usb@f082b000 {
121 compatible = "nuvoton,npcm845-ohci";
122 reg = <0x0 0xF082B000 0x0 0x1000>;
Jim Liuae378012024-01-24 09:54:51 +0800123 resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>;
Jim Liu89b26542022-11-28 10:32:44 +0800124 status = "disabled";
125 };
126
127 usbphy {
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <0>;
131 syscon = <&gcr>;
132 usbphy1: usbphy@1 {
133 compatible = "nuvoton,npcm845-usb-phy";
134 #phy-cells = <1>;
135 reg = <1>;
Jim Liuae378012024-01-24 09:54:51 +0800136 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY1>;
Jim Liu89b26542022-11-28 10:32:44 +0800137 status = "disabled";
138 };
139 usbphy2: usbphy@2 {
140 compatible = "nuvoton,npcm845-usb-phy";
141 #phy-cells = <1>;
142 reg = <2>;
Jim Liuae378012024-01-24 09:54:51 +0800143 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY2>;
Jim Liu89b26542022-11-28 10:32:44 +0800144 status = "disabled";
145 };
146 usbphy3: usbphy@3 {
147 compatible = "nuvoton,npcm845-usb-phy";
148 #phy-cells = <1>;
149 reg = <3>;
Jim Liuae378012024-01-24 09:54:51 +0800150 resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBPHY3>;
Jim Liu89b26542022-11-28 10:32:44 +0800151 status = "disabled";
152 };
153 };
154
155 udc0:udc@f0830100 {
156 compatible = "nuvoton,npcm845-udc";
157 reg = <0x0 0xf0830100 0x0 0x100
158 0x0 0xfffb0000 0x0 0x800>;
159 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clk NPCM8XX_CLK_SU>;
161 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800162 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC0>;
Jim Liu89b26542022-11-28 10:32:44 +0800163 status = "disable";
164 };
165
166 udc1:udc@f0831100 {
167 compatible = "nuvoton,npcm845-udc";
168 reg = <0x0 0xf0831100 0x0 0x100
169 0x0 0xfffb0800 0x0 0x800>;
170 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&clk NPCM8XX_CLK_SU>;
172 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800173 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC1>;
Jim Liu89b26542022-11-28 10:32:44 +0800174 status = "disable";
175 };
176
177 udc2:udc@f0832100 {
178 compatible = "nuvoton,npcm845-udc";
179 reg = <0x0 0xf0832100 0x0 0x100
180 0x0 0xfffb1000 0x0 0x800>;
181 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&clk NPCM8XX_CLK_SU>;
183 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800184 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC2>;
Jim Liu89b26542022-11-28 10:32:44 +0800185 status = "disable";
186 };
187
188 udc3:udc@f0833100 {
189 compatible = "nuvoton,npcm845-udc";
190 reg = <0x0 0xf0833100 0x0 0x100
191 0x0 0xfffb1800 0x0 0x800>;
192 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&clk NPCM8XX_CLK_SU>;
194 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800195 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC3>;
Jim Liu89b26542022-11-28 10:32:44 +0800196 status = "disable";
197 };
198
199 udc4:udc@f0834100 {
200 compatible = "nuvoton,npcm845-udc";
201 reg = <0x0 0xf0834100 0x0 0x100
202 0x0 0xfffb2000 0x0 0x800>;
203 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&clk NPCM8XX_CLK_SU>;
205 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800206 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC4>;
Jim Liu89b26542022-11-28 10:32:44 +0800207 status = "disable";
208 };
209
210 udc5:udc@f0835100 {
211 compatible = "nuvoton,npcm845-udc";
212 reg = <0x0 0xf0835100 0x0 0x100
213 0x0 0xfffb2800 0x0 0x800>;
214 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&clk NPCM8XX_CLK_SU>;
216 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800217 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC5>;
Jim Liu89b26542022-11-28 10:32:44 +0800218 status = "disable";
219 };
220
221 udc6:udc@f0836100 {
222 compatible = "nuvoton,npcm845-udc";
223 reg = <0x0 0xf0836100 0x0 0x100
224 0x0 0xfffb3000 0x0 0x800>;
225 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clk NPCM8XX_CLK_SU>;
227 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800228 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC6>;
Jim Liu89b26542022-11-28 10:32:44 +0800229 status = "disable";
230 };
231
232 udc7:udc@f0837100 {
233 compatible = "nuvoton,npcm845-udc";
234 reg = <0x0 0xf0837100 0x0 0x100
235 0x0 0xfffb3800 0x0 0x800>;
236 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clk NPCM8XX_CLK_SU>;
238 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800239 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC7>;
Jim Liu89b26542022-11-28 10:32:44 +0800240 status = "disable";
241 };
242
243 udc8:udc@f0838100 {
244 compatible = "nuvoton,npcm845-udc";
245 reg = <0x0 0xf0838100 0x0 0x100
246 0x0 0xfffb4000 0x0 0x800>;
247 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clk NPCM8XX_CLK_SU>;
249 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800250 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC8>;
Jim Liu89b26542022-11-28 10:32:44 +0800251 status = "disable";
252 };
253
254 udc9:udc@f0839100 {
255 compatible = "nuvoton,npcm845-udc";
256 reg = <0x0 0xf0839100 0x0 0x100
257 0x0 0xfffb4800 0x0 0x800>;
258 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clk NPCM8XX_CLK_SU>;
260 clock-names = "clk_usb_bridge";
Jim Liuae378012024-01-24 09:54:51 +0800261 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC9>;
Jim Liu89b26542022-11-28 10:32:44 +0800262 status = "disable";
263 };
264
Jim Liu60bfc902023-06-13 15:45:55 +0800265 aes: aes@f0858000 {
266 compatible = "nuvoton,npcm845-aes";
267 reg = <0x0 0xf0858000 0x0 0x1000>,
268 <0x0 0xf0851000 0x0 0x1000>;
269 status = "disabled";
270 clocks = <&clk NPCM8XX_CLK_AHB>;
271 clock-names = "clk_ahb";
272 };
273
274 sha:sha@f085a000 {
275 compatible = "nuvoton,npcm845-sha";
276 reg = <0x0 0xf085a000 0x0 0x1000>;
277 status = "disabled";
278 clocks = <&clk NPCM8XX_CLK_AHB>;
279 clock-names = "clk_ahb";
280 };
281
Jim Liu147c0002022-09-27 16:45:15 +0800282 apb {
283 serial0: serial@0 {
284 compatible = "nuvoton,npcm845-uart";
285 reg = <0x0 0x1000>;
286 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
287 clock-frequency = <24000000>;
288 status = "disabled";
289 };
290
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800291 serial1: serial@1000 {
292 compatible = "nuvoton,npcm845-uart";
293 reg = <0x1000 0x1000>;
294 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
295 status = "disabled";
296 };
297
298 serial2: serial@2000 {
299 compatible = "nuvoton,npcm845-uart";
300 reg = <0x2000 0x1000>;
301 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
302 status = "disabled";
303 };
304
305 serial3: serial@3000 {
306 compatible = "nuvoton,npcm845-uart";
307 reg = <0x3000 0x1000>;
308 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
309 status = "disabled";
310 };
311
312 serial4: serial@4000 {
313 compatible = "nuvoton,npcm845-uart";
314 reg = <0x4000 0x1000>;
315 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
316 status = "disabled";
317 };
318
319 serial5: serial@5000 {
320 compatible = "nuvoton,npcm845-uart";
321 reg = <0x5000 0x1000>;
322 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
323 status = "disabled";
324 };
325
326 serial6: serial@6000 {
327 compatible = "nuvoton,npcm845-uart";
328 reg = <0x6000 0x1000>;
329 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
330 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
331 status = "disabled";
332 };
333
Jim Liu147c0002022-09-27 16:45:15 +0800334 gpio0: gpio0@10000 {
Jim Liu89b26542022-11-28 10:32:44 +0800335 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800336 reg = <0x10000 0xB0>;
337 #gpio-cells = <2>;
338 gpio-controller;
339 gpio-bank-name = "gpio0";
340 };
341
342 gpio1: gpio1@11000 {
Jim Liu89b26542022-11-28 10:32:44 +0800343 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800344 reg = <0x11000 0xB0>;
345 #gpio-cells = <2>;
346 gpio-controller;
347 gpio-bank-name = "gpio1";
348 };
349
350 gpio2: gpio2@12000 {
Jim Liu89b26542022-11-28 10:32:44 +0800351 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800352 reg = <0x12000 0xB0>;
353 #gpio-cells = <2>;
354 gpio-controller;
355 gpio-bank-name = "gpio2";
356 };
357
358 gpio3: gpio3@13000 {
Jim Liu89b26542022-11-28 10:32:44 +0800359 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800360 reg = <0x13000 0xB0>;
361 #gpio-cells = <2>;
362 gpio-controller;
363 gpio-bank-name = "gpio3";
364 };
365
366 gpio4: gpio4@14000 {
Jim Liu89b26542022-11-28 10:32:44 +0800367 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800368 reg = <0x14000 0xB0>;
369 #gpio-cells = <2>;
370 gpio-controller;
371 gpio-bank-name = "gpio4";
372 };
373
374 gpio5: gpio5@15000 {
Jim Liu89b26542022-11-28 10:32:44 +0800375 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800376 reg = <0x15000 0xB0>;
377 #gpio-cells = <2>;
378 gpio-controller;
379 gpio-bank-name = "gpio5";
380 };
381
382 gpio6: gpio6@16000 {
Jim Liu89b26542022-11-28 10:32:44 +0800383 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800384 reg = <0x16000 0xB0>;
385 #gpio-cells = <2>;
386 gpio-controller;
387 gpio-bank-name = "gpio6";
388 };
389
390 gpio7: gpio7@17000 {
Jim Liu89b26542022-11-28 10:32:44 +0800391 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800392 reg = <0x17000 0xB0>;
393 #gpio-cells = <2>;
394 gpio-controller;
395 gpio-bank-name = "gpio7";
396 };
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800397
398 rng: rng@b000 {
399 compatible = "nuvoton,npcm845-rng";
400 reg = <0xb000 0x8>;
401 status = "disabled";
402 };
403
404 otp: otp@189000 {
405 compatible = "nuvoton,npcm845-otp";
406 reg = <0x189000 0x1000>;
407 status = "disabled";
408 };
409
Jim Liu147c0002022-09-27 16:45:15 +0800410 };
411 };
Jim Liu89b26542022-11-28 10:32:44 +0800412 pinctrl: pinctrl@f0800000 {
413 compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd";
414 reg = <0x0 0xf0010000 0x0 0x8000>;
415 syscon-gcr = <&gcr>;
416 syscon-rst = <&rstc>;
417 status = "okay";
418
419 iox1_pins: iox1-pins {
420 groups = "iox1";
421 function = "iox1";
422 };
423 iox2_pins: iox2-pins {
424 groups = "iox2";
425 function = "iox2";
426 };
427 smb1d_pins: smb1d-pins {
428 groups = "smb1d";
429 function = "smb1d";
430 };
431 smb2d_pins: smb2d-pins {
432 groups = "smb2d";
433 function = "smb2d";
434 };
435 lkgpo1_pins: lkgpo1-pins {
436 groups = "lkgpo1";
437 function = "lkgpo1";
438 };
439 lkgpo2_pins: lkgpo2-pins {
440 groups = "lkgpo2";
441 function = "lkgpo2";
442 };
443 ioxh_pins: ioxh-pins {
444 groups = "ioxh";
445 function = "ioxh";
446 };
447 gspi_pins: gspi-pins {
448 groups = "gspi";
449 function = "gspi";
450 };
451 smb5b_pins: smb5b-pins {
452 groups = "smb5b";
453 function = "smb5b";
454 };
455 smb5c_pins: smb5c-pins {
456 groups = "smb5c";
457 function = "smb5c";
458 };
459 lkgpo0_pins: lkgpo0-pins {
460 groups = "lkgpo0";
461 function = "lkgpo0";
462 };
463 pspi_pins: pspi-pins {
464 groups = "pspi";
465 function = "pspi";
466 };
467 vgadig_pins: vgadig-pins {
468 groups = "vgadig";
469 function = "vgadig";
470 };
471 jm1_pins: jm1-pins {
472 groups = "jm1";
473 function = "jm1";
474 };
475 jm2_pins: jm2-pins {
476 groups = "jm2";
477 function = "jm2";
478 };
479 smb4b_pins: smb4b-pins {
480 groups = "smb4b";
481 function = "smb4b";
482 };
483 smb4c_pins: smb4c-pins {
484 groups = "smb4c";
485 function = "smb4c";
486 };
487 smb15_pins: smb15-pins {
488 groups = "smb15";
489 function = "smb15";
490 };
491 smb16_pins: smb16-pins {
492 groups = "smb16";
493 function = "smb16";
494 };
495 smb17_pins: smb17-pins {
496 groups = "smb17";
497 function = "smb17";
498 };
499 smb18_pins: smb18-pins {
500 groups = "smb18";
501 function = "smb18";
502 };
503 smb19_pins: smb19-pins {
504 groups = "smb19";
505 function = "smb19";
506 };
507 smb20_pins: smb20-pins {
508 groups = "smb20";
509 function = "smb20";
510 };
511 smb21_pins: smb21-pins {
512 groups = "smb21";
513 function = "smb21";
514 };
515 smb22_pins: smb22-pins {
516 groups = "smb22";
517 function = "smb22";
518 };
519 smb23_pins: smb23-pins {
520 groups = "smb23";
521 function = "smb23";
522 };
523 smb4d_pins: smb4d-pins {
524 groups = "smb4d";
525 function = "smb4d";
526 };
527 smb14_pins: smb14-pins {
528 groups = "smb14";
529 function = "smb14";
530 };
531 smb5_pins: smb5-pins {
532 groups = "smb5";
533 function = "smb5";
534 };
535 smb4_pins: smb4-pins {
536 groups = "smb4";
537 function = "smb4";
538 };
539 smb3_pins: smb3-pins {
540 groups = "smb3";
541 function = "smb3";
542 };
543 spi0cs1_pins: spi0cs1-pins {
544 groups = "spi0cs1";
545 function = "spi0cs1";
546 };
547 spi0cs2_pins: spi0cs2-pins {
548 groups = "spi0cs2";
549 function = "spi0cs2";
550 };
551 spi0cs3_pins: spi0cs3-pins {
552 groups = "spi0cs3";
553 function = "spi0cs3";
554 };
555 smb3c_pins: smb3c-pins {
556 groups = "smb3c";
557 function = "smb3c";
558 };
559 smb3b_pins: smb3b-pins {
560 groups = "smb3b";
561 function = "smb3b";
562 };
563 hsi1a_pins: hsi1a-pins {
564 groups = "hsi1a";
565 function = "hsi1a";
566 };
567 hsi1b_pins: hsi1b-pins {
568 groups = "hsi1b";
569 function = "hsi1b";
570 };
571 hsi1c_pins: hsi1c-pins {
572 groups = "hsi1c";
573 function = "hsi1c";
574 };
575 hsi2a_pins: hsi2a-pins {
576 groups = "hsi2a";
577 function = "hsi2a";
578 };
579 hsi2b_pins: hsi2b-pins {
580 groups = "hsi2b";
581 function = "hsi2b";
582 };
583 hsi2c_pins: hsi2c-pins {
584 groups = "hsi2c";
585 function = "hsi2c";
586 };
587 bmcuart0a_pins: bmcuart0a-pins {
588 groups = "bmcuart0a";
589 function = "bmcuart0a";
590 };
591 bmcuart0b_pins: bmcuart0b-pins {
592 groups = "bmcuart0b";
593 function = "bmcuart0b";
594 };
595 bmcuart1_pins: bmcuart1-pins {
596 groups = "bmcuart1";
597 function = "bmcuart1";
598 };
599 bu4_pins: bu4-pins {
600 groups = "bu4";
601 function = "bu4";
602 };
603 bu5_pins: bu5-pins {
604 groups = "bu5";
605 function = "bu5";
606 };
607 bu6_pins: bu6-pins {
608 groups = "bu6";
609 function = "bu6";
610 };
611 r1err_pins: r1err-pins {
612 groups = "r1err";
613 function = "r1err";
614 };
615 r1md_pins: r1md-pins {
616 groups = "r1md";
617 function = "r1md";
618 };
619 r1oen_pins: r1oen-pins {
620 groups = "r1oen";
621 function = "r1oen";
622 };
623 r1en_pins: r1en-pins {
624 groups = "r1en";
625 function = "r1en";
626 };
627 r2oen_pins: r2oen-pins {
628 groups = "r2oen";
629 function = "r2oen";
630 };
631 r2en_pins: r2en-pins {
632 groups = "r2en";
633 function = "r2en";
634 };
635 rmii3_pins: rmii3_pins {
636 groups = "rmii3";
637 function = "rmii3";
638 };
639 r3oen_pins: r3oen-pins {
640 groups = "r3oen";
641 function = "r3oen";
642 };
643 r3en_pins: r3en-pins {
644 groups = "r3en";
645 function = "r3en";
646 };
647 smb3d_pins: smb3d-pins {
648 groups = "smb3d";
649 function = "smb3d";
650 };
651 fanin0_pins: fanin0-pins {
652 groups = "fanin0";
653 function = "fanin0";
654 };
655 fanin1_pins: fanin1-pins {
656 groups = "fanin1";
657 function = "fanin1";
658 };
659 fanin2_pins: fanin2-pins {
660 groups = "fanin2";
661 function = "fanin2";
662 };
663 fanin3_pins: fanin3-pins {
664 groups = "fanin3";
665 function = "fanin3";
666 };
667 fanin4_pins: fanin4-pins {
668 groups = "fanin4";
669 function = "fanin4";
670 };
671 fanin5_pins: fanin5-pins {
672 groups = "fanin5";
673 function = "fanin5";
674 };
675 fanin6_pins: fanin6-pins {
676 groups = "fanin6";
677 function = "fanin6";
678 };
679 fanin7_pins: fanin7-pins {
680 groups = "fanin7";
681 function = "fanin7";
682 };
683 fanin8_pins: fanin8-pins {
684 groups = "fanin8";
685 function = "fanin8";
686 };
687 fanin9_pins: fanin9-pins {
688 groups = "fanin9";
689 function = "fanin9";
690 };
691 fanin10_pins: fanin10-pins {
692 groups = "fanin10";
693 function = "fanin10";
694 };
695 fanin11_pins: fanin11-pins {
696 groups = "fanin11";
697 function = "fanin11";
698 };
699 fanin12_pins: fanin12-pins {
700 groups = "fanin12";
701 function = "fanin12";
702 };
703 fanin13_pins: fanin13-pins {
704 groups = "fanin13";
705 function = "fanin13";
706 };
707 fanin14_pins: fanin14-pins {
708 groups = "fanin14";
709 function = "fanin14";
710 };
711 fanin15_pins: fanin15-pins {
712 groups = "fanin15";
713 function = "fanin15";
714 };
715 pwm0_pins: pwm0-pins {
716 groups = "pwm0";
717 function = "pwm0";
718 };
719 pwm1_pins: pwm1-pins {
720 groups = "pwm1";
721 function = "pwm1";
722 };
723 pwm2_pins: pwm2-pins {
724 groups = "pwm2";
725 function = "pwm2";
726 };
727 pwm3_pins: pwm3-pins {
728 groups = "pwm3";
729 function = "pwm3";
730 };
731 r2_pins: r2-pins {
732 groups = "r2";
733 function = "r2";
734 };
735 r2err_pins: r2err-pins {
736 groups = "r2err";
737 function = "r2err";
738 };
739 r2md_pins: r2md-pins {
740 groups = "r2md";
741 function = "r2md";
742 };
743 r3rxer_pins: r3rxer_pins {
744 groups = "r3rxer";
745 function = "r3rxer";
746 };
747 ga20kbc_pins: ga20kbc-pins {
748 groups = "ga20kbc";
749 function = "ga20kbc";
750 };
751 smb5d_pins: smb5d-pins {
752 groups = "smb5d";
753 function = "smb5d";
754 };
755 lpc_pins: lpc-pins {
756 groups = "lpc";
757 function = "lpc";
758 };
759 espi_pins: espi-pins {
760 groups = "espi";
761 function = "espi";
762 };
763 rg1_pins: rg1-pins {
764 groups = "rg1";
765 function = "rg1";
766 };
767 rg1mdio_pins: rg1mdio-pins {
768 groups = "rg1mdio";
769 function = "rg1mdio";
770 };
771 rg2_pins: rg2-pins {
772 groups = "rg2";
773 function = "rg2";
774 };
775 ddr_pins: ddr-pins {
776 groups = "ddr";
777 function = "ddr";
778 };
779 i3c0_pins: i3c0-pins {
780 groups = "i3c0";
781 function = "i3c0";
782 };
783 i3c1_pins: i3c1-pins {
784 groups = "i3c1";
785 function = "i3c1";
786 };
787 i3c2_pins: i3c2-pins {
788 groups = "i3c2";
789 function = "i3c2";
790 };
791 i3c3_pins: i3c3-pins {
792 groups = "i3c3";
793 function = "i3c3";
794 };
795 i3c4_pins: i3c4-pins {
796 groups = "i3c4";
797 function = "i3c4";
798 };
799 i3c5_pins: i3c5-pins {
800 groups = "i3c5";
801 function = "i3c5";
802 };
803 smb0_pins: smb0-pins {
804 groups = "smb0";
805 function = "smb0";
806 };
807 smb1_pins: smb1-pins {
808 groups = "smb1";
809 function = "smb1";
810 };
811 smb2_pins: smb2-pins {
812 groups = "smb2";
813 function = "smb2";
814 };
815 smb2c_pins: smb2c-pins {
816 groups = "smb2c";
817 function = "smb2c";
818 };
819 smb2b_pins: smb2b-pins {
820 groups = "smb2b";
821 function = "smb2b";
822 };
823 smb1c_pins: smb1c-pins {
824 groups = "smb1c";
825 function = "smb1c";
826 };
827 smb1b_pins: smb1b-pins {
828 groups = "smb1b";
829 function = "smb1b";
830 };
831 smb8_pins: smb8-pins {
832 groups = "smb8";
833 function = "smb8";
834 };
835 smb9_pins: smb9-pins {
836 groups = "smb9";
837 function = "smb9";
838 };
839 smb10_pins: smb10-pins {
840 groups = "smb10";
841 function = "smb10";
842 };
843 smb11_pins: smb11-pins {
844 groups = "smb11";
845 function = "smb11";
846 };
847 sd1_pins: sd1-pins {
848 groups = "sd1";
849 function = "sd1";
850 };
851 sd1pwr_pins: sd1pwr-pins {
852 groups = "sd1pwr";
853 function = "sd1pwr";
854 };
855 pwm4_pins: pwm4-pins {
856 groups = "pwm4";
857 function = "pwm4";
858 };
859 pwm5_pins: pwm5-pins {
860 groups = "pwm5";
861 function = "pwm5";
862 };
863 pwm6_pins: pwm6-pins {
864 groups = "pwm6";
865 function = "pwm6";
866 };
867 pwm7_pins: pwm7-pins {
868 groups = "pwm7";
869 function = "pwm7";
870 };
871 pwm8_pins: pwm8-pins {
872 groups = "pwm8";
873 function = "pwm8";
874 };
875 pwm9_pins: pwm9-pins {
876 groups = "pwm9";
877 function = "pwm9";
878 };
879 pwm10_pins: pwm10-pins {
880 groups = "pwm10";
881 function = "pwm10";
882 };
883 pwm11_pins: pwm11-pins {
884 groups = "pwm11";
885 function = "pwm11";
886 };
887 mmc8_pins: mmc8-pins {
888 groups = "mmc8";
889 function = "mmc8";
890 };
891 mmc_pins: mmc-pins {
892 groups = "mmc";
893 function = "mmc";
894 };
895 mmcwp_pins: mmcwp-pins {
896 groups = "mmcwp";
897 function = "mmcwp";
898 };
899 mmccd_pins: mmccd-pins {
900 groups = "mmccd";
901 function = "mmccd";
902 };
903 mmcrst_pins: mmcrst-pins {
904 groups = "mmcrst";
905 function = "mmcrst";
906 };
907 clkout_pins: clkout-pins {
908 groups = "clkout";
909 function = "clkout";
910 };
911 serirq_pins: serirq-pins {
912 groups = "serirq";
913 function = "serirq";
914 };
915 scipme_pins: scipme-pins {
916 groups = "scipme";
917 function = "scipme";
918 };
919 sci_pins: sci-pins {
920 groups = "sci";
921 function = "sci";
922 };
923 smb6_pins: smb6-pins {
924 groups = "smb6";
925 function = "smb6";
926 };
927 smb7_pins: smb7-pins {
928 groups = "smb7";
929 function = "smb7";
930 };
931 spi1_pins: spi1-pins {
932 groups = "spi1";
933 function = "spi1";
934 };
935 spi1d23_pins: spi1d23-pins {
936 groups = "spi1d23";
937 function = "spi1d23";
938 };
939 faninx_pins: faninx-pins {
940 groups = "faninx";
941 function = "faninx";
942 };
943 r1_pins: r1-pins {
944 groups = "r1";
945 function = "r1";
946 };
947 spi3_pins: spi3-pins {
948 groups = "spi3";
949 function = "spi3";
950 };
951 spi3cs1_pins: spi3cs1-pins {
952 groups = "spi3cs1";
953 function = "spi3cs1";
954 };
955 spi3quad_pins: spi3quad-pins {
956 groups = "spi3quad";
957 function = "spi3quad";
958 };
959 spi3cs2_pins: spi3cs2-pins {
960 groups = "spi3cs2";
961 function = "spi3cs2";
962 };
963 spi3cs3_pins: spi3cs3-pins {
964 groups = "spi3cs3";
965 function = "spi3cs3";
966 };
967 nprd_smi_pins: nprd-smi-pins {
968 groups = "nprd_smi";
969 function = "nprd_smi";
970 };
971 smb0b_pins: smb0b-pins {
972 groups = "smb0b";
973 function = "smb0b";
974 };
975 smb0c_pins: smb0c-pins {
976 groups = "smb0c";
977 function = "smb0c";
978 };
979 smb0den_pins: smb0den-pins {
980 groups = "smb0den";
981 function = "smb0den";
982 };
983 smb0d_pins: smb0d-pins {
984 groups = "smb0d";
985 function = "smb0d";
986 };
987 rg2mdio_pins: rg2mdio-pins {
988 groups = "rg2mdio";
989 function = "rg2mdio";
990 };
991 rg2refck_pins: rg2refck-pins {
992 groups = "rg2refck";
993 function = "rg2refck";
994 };
995 wdog1_pins: wdog1-pins {
996 groups = "wdog1";
997 function = "wdog1";
998 };
999 wdog2_pins: wdog2-pins {
1000 groups = "wdog2";
1001 function = "wdog2";
1002 };
1003 smb12_pins: smb12-pins {
1004 groups = "smb12";
1005 function = "smb12";
1006 };
1007 smb13_pins: smb13-pins {
1008 groups = "smb13";
1009 function = "smb13";
1010 };
1011 spix_pins: spix-pins {
1012 groups = "spix";
1013 function = "spix";
1014 };
1015 spixcs1_pins: spixcs1-pins {
1016 groups = "spixcs1";
1017 function = "spixcs1";
1018 };
1019 clkreq_pins: clkreq-pins {
1020 groups = "clkreq";
1021 function = "clkreq";
1022 };
1023 hgpio0_pins: hgpio0-pins {
1024 groups = "hgpio0";
1025 function = "hgpio0";
1026 };
1027 hgpio1_pins: hgpio1-pins {
1028 groups = "hgpio1";
1029 function = "hgpio1";
1030 };
1031 hgpio2_pins: hgpio2-pins {
1032 groups = "hgpio2";
1033 function = "hgpio2";
1034 };
1035 hgpio3_pins: hgpio3-pins {
1036 groups = "hgpio3";
1037 function = "hgpio3";
1038 };
1039 hgpio4_pins: hgpio4-pins {
1040 groups = "hgpio4";
1041 function = "hgpio4";
1042 };
1043 hgpio5_pins: hgpio5-pins {
1044 groups = "hgpio5";
1045 function = "hgpio5";
1046 };
1047 hgpio6_pins: hgpio6-pins {
1048 groups = "hgpio6";
1049 function = "hgpio6";
1050 };
1051 hgpio7_pins: hgpio7-pins {
1052 groups = "hgpio7";
1053 function = "hgpio7";
1054 };
1055 jtag2_pins: jtag2-pins {
1056 groups = "jtag2";
1057 function = "jtag2";
1058 };
1059 };
Jim Liu147c0002022-09-27 16:45:15 +08001060};