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git01.mediatek.com / filogic / uboot / adda11160346c765b10c71c9d71e465a4185ff50 / . / arch / arm / dts / k3-am642-evm-u-boot.dtsi
blob: 705b3baa81cfbdc7eb532a59fb8ff5aad9e3990f [file] [log] [blame]
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10 tick-timer = &main_timer0;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]11 };
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]12};
13
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]14&main_timer0 {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]15 clock-frequency = <200000000>;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]16};
17
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]18&usb0 {
19 dr_mode="peripheral";
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]20};
21
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]22&main_mmc1_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]23 bootph-all;
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]24};
25
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]26&sdhci0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]27 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]28};
29
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]30&main_mmc1_pins_default {
31 bootph-all;
32};
33
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]34&inta_main_dmss {
35 bootph-all;
36};
37
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]38&main_bcdma {
39 reg = <0x00 0x485c0100 0x00 0x100>,
40 <0x00 0x4c000000 0x00 0x20000>,
41 <0x00 0x4a820000 0x00 0x20000>,
42 <0x00 0x4aa40000 0x00 0x20000>,
43 <0x00 0x4bc00000 0x00 0x100000>,
44 <0x00 0x48600000 0x00 0x8000>,
45 <0x00 0x484a4000 0x00 0x2000>,
46 <0x00 0x484c2000 0x00 0x2000>;
47 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
48 "cfg", "tchan", "rchan";
49};
50
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]51&main_pktdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]52 reg = <0x00 0x485c0000 0x00 0x100>,
53 <0x00 0x4a800000 0x00 0x20000>,
54 <0x00 0x4aa00000 0x00 0x40000>,
55 <0x00 0x4b800000 0x00 0x400000>,
56 <0x00 0x485e0000 0x00 0x20000>,
57 <0x00 0x484a0000 0x00 0x4000>,
58 <0x00 0x484c0000 0x00 0x2000>,
59 <0x00 0x48430000 0x00 0x4000>;
60 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
61 "tchan", "rchan", "rflow";
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]62 bootph-all;
63};
64
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]65&cpsw_port2 {
66 status = "disabled";
67};
Jonathan Humphreyse1ce4f42024-02-23 18:17:02 -0600[diff] [blame]68
69&ospi0_pins_default {
70 bootph-all;
71};
72
73&fss {
74 bootph-all;
75};
76
77&ospi0 {
78 bootph-all;
79
80 flash@0 {
81 bootph-all;
82 };
83};