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git01.mediatek.com / filogic / uboot / adda11160346c765b10c71c9d71e465a4185ff50 / . / arch / arm / dts / fsl-imx8qxp-colibri-u-boot.dtsi
blob: 60c4cd6fc01ffca2e48d21df09b8a249af2c91f2 [file] [log] [blame]
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Toradex AG
4 */
5
Emanuele Ghidoli26b5cba2024-02-23 10:11:41 +0100[diff] [blame]6/ {
7 sysinfo {
8 compatible = "toradex,sysinfo";
9 };
10};
11
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]12&{/imx8qx-pm} {
13
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]14 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]15};
16
17&mu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]19};
20
21&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]23};
24
25&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]27};
28
29&pd_lsio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]31};
32
33&pd_lsio_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]35};
36
37&pd_lsio_gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]39};
40
41&pd_lsio_gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]43};
44
45&pd_lsio_gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]47};
48
49&pd_lsio_gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]51};
52
53&pd_lsio_gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]55};
56
57&pd_lsio_gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]59};
60
61&pd_lsio_gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]63};
64
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]65&pd_dma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]67};
68
69&pd_dma_lpuart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]71};
72
73&pd_dma_lpuart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]75};
76
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]77&pd_conn {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]79};
80
81&pd_conn_sdch0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]83};
84
85&pd_conn_sdch1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]87};
88
89&pd_conn_sdch2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]91};
92
Andrejs Cainikovs720cdc52023-12-20 11:38:11 +0100[diff] [blame]93&gpio_expander_43 {
94 usb-bypass-n-hog {
95 gpio-hog;
96 gpios = <5 GPIO_ACTIVE_LOW>;
97 line-name = "usb-bypass-n";
98 output-high;
99 };
100 usb-reset-n-hog {
101 gpio-hog;
102 gpios = <4 GPIO_ACTIVE_LOW>;
103 line-name = "usb-reset-n";
104 output-low;
105 };
106};
107
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]108&gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]110};
111
112&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]114};
115
116&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]118};
119
120&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]122};
123
124&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]126};
127
128&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]130};
131
132&gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]133 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]134};
135
136&gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]137 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]138};
139
140&lpuart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]142};
143
144&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]145 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]146};
147
148&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]149 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]150};