blob: e95f4631bf2f8296f2a113b71706094423fee7e2 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04005#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05306#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01007
Simon Glassb2c1cac2014-02-26 15:59:21 -07008/ {
9 model = "sandbox";
10 compatible = "sandbox";
11 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060012 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070013
Simon Glassfef72b72014-07-23 06:55:03 -060014 aliases {
15 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070017 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060018 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060019 gpio1 = &gpio_a;
20 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010021 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070022 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060023 mmc0 = "/mmc0";
24 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070025 pci0 = &pci0;
26 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070027 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020028 remoteproc0 = &rproc_1;
29 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060030 rtc0 = &rtc_0;
31 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060032 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020033 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070034 testbus3 = "/some-bus";
35 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070036 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testfdt3 = "/b-test";
38 testfdt5 = "/some-bus/c-test@5";
39 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070040 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020041 fdt-dummy0 = "/translation-test@8000/dev@0,0";
42 fdt-dummy1 = "/translation-test@8000/dev@1,100";
43 fdt-dummy2 = "/translation-test@8000/dev@2,200";
44 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchib574d682020-12-30 00:16:21 +010045 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glass31680482015-03-25 12:23:05 -060046 usb0 = &usb_0;
47 usb1 = &usb_1;
48 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020049 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020050 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060051 };
52
Simon Glassed96cde2018-12-10 10:37:33 -070053 audio: audio-codec {
54 compatible = "sandbox,audio-codec";
55 #sound-dai-cells = <1>;
56 };
57
Philippe Reynes1ee26482020-07-24 18:19:51 +020058 buttons {
59 compatible = "gpio-keys";
60
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020061 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020062 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020063 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020064 };
65
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020066 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020067 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020068 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020069 };
70 };
71
Simon Glassc953aaf2018-12-10 10:37:34 -070072 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060073 reg = <0 0>;
74 compatible = "google,cros-ec-sandbox";
75
76 /*
77 * This describes the flash memory within the EC. Note
78 * that the STM32L flash erases to 0, not 0xff.
79 */
80 flash {
81 image-pos = <0x08000000>;
82 size = <0x20000>;
83 erase-value = <0>;
84
85 /* Information for sandbox */
86 ro {
87 image-pos = <0>;
88 size = <0xf000>;
89 };
90 wp-ro {
91 image-pos = <0xf000>;
92 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -070093 used = <0x884>;
94 compress = "lz4";
95 uncomp-size = <0xcf8>;
96 hash {
97 algo = "sha256";
98 value = [00 01 02 03 04 05 06 07
99 08 09 0a 0b 0c 0d 0e 0f
100 10 11 12 13 14 15 16 17
101 18 19 1a 1b 1c 1d 1e 1f];
102 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600103 };
104 rw {
105 image-pos = <0x10000>;
106 size = <0x10000>;
107 };
108 };
109 };
110
Yannick Fertré9712c822019-10-07 15:29:05 +0200111 dsi_host: dsi_host {
112 compatible = "sandbox,dsi-host";
113 };
114
Simon Glassb2c1cac2014-02-26 15:59:21 -0700115 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600116 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700117 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600118 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700119 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600120 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100121 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
122 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700123 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100124 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
125 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
126 <&gpio_b 7 GPIO_IN 3 2 1>,
127 <&gpio_b 8 GPIO_OUT 3 2 1>,
128 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100129 test3-gpios =
130 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
131 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
132 <&gpio_c 2 GPIO_OUT>,
133 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
134 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200135 <&gpio_c 5 GPIO_IN>,
136 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
137 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530138 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
139 test5-gpios = <&gpio_a 19>;
140
Simon Glass6df01f92018-12-10 10:37:37 -0700141 int-value = <1234>;
142 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200143 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200144 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600145 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700146 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600147 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200148 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530149
150 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
151 <&muxcontroller0 2>, <&muxcontroller0 3>,
152 <&muxcontroller1>;
153 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
154 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100155 display-timings {
156 timing0: 240x320 {
157 clock-frequency = <6500000>;
158 hactive = <240>;
159 vactive = <320>;
160 hfront-porch = <6>;
161 hback-porch = <7>;
162 hsync-len = <1>;
163 vback-porch = <5>;
164 vfront-porch = <8>;
165 vsync-len = <2>;
166 hsync-active = <1>;
167 vsync-active = <0>;
168 de-active = <1>;
169 pixelclk-active = <1>;
170 interlaced;
171 doublescan;
172 doubleclk;
173 };
174 timing1: 480x800 {
175 clock-frequency = <9000000>;
176 hactive = <480>;
177 vactive = <800>;
178 hfront-porch = <10>;
179 hback-porch = <59>;
180 hsync-len = <12>;
181 vback-porch = <15>;
182 vfront-porch = <17>;
183 vsync-len = <16>;
184 hsync-active = <0>;
185 vsync-active = <1>;
186 de-active = <0>;
187 pixelclk-active = <0>;
188 };
189 timing2: 800x480 {
190 clock-frequency = <33500000>;
191 hactive = <800>;
192 vactive = <480>;
193 hback-porch = <89>;
194 hfront-porch = <164>;
195 vback-porch = <23>;
196 vfront-porch = <10>;
197 hsync-len = <11>;
198 vsync-len = <13>;
199 };
200 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700201 };
202
203 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600204 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700205 compatible = "not,compatible";
206 };
207
208 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600209 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700210 };
211
Simon Glass5620cf82018-10-01 12:22:40 -0600212 backlight: backlight {
213 compatible = "pwm-backlight";
214 enable-gpios = <&gpio_a 1>;
215 power-supply = <&ldo_1>;
216 pwms = <&pwm 0 1000>;
217 default-brightness-level = <5>;
218 brightness-levels = <0 16 32 64 128 170 202 234 255>;
219 };
220
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200221 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200222 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200223 bind-test-child1 {
224 compatible = "sandbox,phy";
225 #phy-cells = <1>;
226 };
227
228 bind-test-child2 {
229 compatible = "simple-bus";
230 };
231 };
232
Simon Glassb2c1cac2014-02-26 15:59:21 -0700233 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600234 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700235 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600236 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700237 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530238
239 mux-controls = <&muxcontroller0 0>;
240 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700241 };
242
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200243 phy_provider0: gen_phy@0 {
244 compatible = "sandbox,phy";
245 #phy-cells = <1>;
246 };
247
248 phy_provider1: gen_phy@1 {
249 compatible = "sandbox,phy";
250 #phy-cells = <0>;
251 broken;
252 };
253
developer71092972020-05-02 11:35:12 +0200254 phy_provider2: gen_phy@2 {
255 compatible = "sandbox,phy";
256 #phy-cells = <0>;
257 };
258
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200259 gen_phy_user: gen_phy_user {
260 compatible = "simple-bus";
261 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
262 phy-names = "phy1", "phy2", "phy3";
263 };
264
developer71092972020-05-02 11:35:12 +0200265 gen_phy_user1: gen_phy_user1 {
266 compatible = "simple-bus";
267 phys = <&phy_provider0 0>, <&phy_provider2>;
268 phy-names = "phy1", "phy2";
269 };
270
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 some-bus {
272 #address-cells = <1>;
273 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600274 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600275 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600276 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700277 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600278 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700279 compatible = "denx,u-boot-fdt-test";
280 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600281 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700282 ping-add = <5>;
283 };
Simon Glass40717422014-07-23 06:55:18 -0600284 c-test@0 {
285 compatible = "denx,u-boot-fdt-test";
286 reg = <0>;
287 ping-expect = <6>;
288 ping-add = <6>;
289 };
290 c-test@1 {
291 compatible = "denx,u-boot-fdt-test";
292 reg = <1>;
293 ping-expect = <7>;
294 ping-add = <7>;
295 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700296 };
297
298 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600299 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600300 ping-expect = <6>;
301 ping-add = <6>;
302 compatible = "google,another-fdt-test";
303 };
304
305 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600306 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600307 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700308 ping-add = <6>;
309 compatible = "google,another-fdt-test";
310 };
311
Simon Glass0ccb0972015-01-25 08:27:05 -0700312 f-test {
313 compatible = "denx,u-boot-fdt-test";
314 };
315
316 g-test {
317 compatible = "denx,u-boot-fdt-test";
318 };
319
Bin Mengd9d24782018-10-10 22:07:01 -0700320 h-test {
321 compatible = "denx,u-boot-fdt-test1";
322 };
323
developercf8bc132020-05-02 11:35:10 +0200324 i-test {
325 compatible = "mediatek,u-boot-fdt-test";
326 #address-cells = <1>;
327 #size-cells = <0>;
328
329 subnode@0 {
330 reg = <0>;
331 };
332
333 subnode@1 {
334 reg = <1>;
335 };
336
337 subnode@2 {
338 reg = <2>;
339 };
340 };
341
Simon Glass204675c2019-12-29 21:19:25 -0700342 devres-test {
343 compatible = "denx,u-boot-devres-test";
344 };
345
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530346 another-test {
347 reg = <0 2>;
348 compatible = "denx,u-boot-fdt-test";
349 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
350 test5-gpios = <&gpio_a 19>;
351 };
352
Simon Glass3c601b12020-07-07 13:12:06 -0600353 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600354 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600355 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600356 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600357 child {
358 compatible = "denx,u-boot-acpi-test";
359 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600360 };
361
Simon Glass3c601b12020-07-07 13:12:06 -0600362 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600363 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600364 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600365 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600366 };
367
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200368 clocks {
369 clk_fixed: clk-fixed {
370 compatible = "fixed-clock";
371 #clock-cells = <0>;
372 clock-frequency = <1234>;
373 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000374
375 clk_fixed_factor: clk-fixed-factor {
376 compatible = "fixed-factor-clock";
377 #clock-cells = <0>;
378 clock-div = <3>;
379 clock-mult = <2>;
380 clocks = <&clk_fixed>;
381 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200382
383 osc {
384 compatible = "fixed-clock";
385 #clock-cells = <0>;
386 clock-frequency = <20000000>;
387 };
Stephen Warrena9622432016-06-17 09:44:00 -0600388 };
389
390 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600391 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600392 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200393 assigned-clocks = <&clk_sandbox 3>;
394 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600395 };
396
397 clk-test {
398 compatible = "sandbox,clk-test";
399 clocks = <&clk_fixed>,
400 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200401 <&clk_sandbox 0>,
402 <&clk_sandbox 3>,
403 <&clk_sandbox 2>;
404 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600405 };
406
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200407 ccf: clk-ccf {
408 compatible = "sandbox,clk-ccf";
409 };
410
Simon Glass5b968632015-05-22 15:42:15 -0600411 eth@10002000 {
412 compatible = "sandbox,eth";
413 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500414 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600415 };
416
417 eth_5: eth@10003000 {
418 compatible = "sandbox,eth";
419 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500420 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600421 };
422
Bin Meng04a11cb2015-08-27 22:25:53 -0700423 eth_3: sbe5 {
424 compatible = "sandbox,eth";
425 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500426 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700427 };
428
Simon Glass5b968632015-05-22 15:42:15 -0600429 eth@10004000 {
430 compatible = "sandbox,eth";
431 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500432 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600433 };
434
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700435 firmware {
436 sandbox_firmware: sandbox-firmware {
437 compatible = "sandbox,firmware";
438 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200439
440 sandbox-scmi-agent@0 {
441 compatible = "sandbox,scmi-agent";
442 #address-cells = <1>;
443 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200444
445 clk_scmi0: protocol@14 {
446 reg = <0x14>;
447 #clock-cells = <1>;
448 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200449
450 reset_scmi0: protocol@16 {
451 reg = <0x16>;
452 #reset-cells = <1>;
453 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200454 };
455
456 sandbox-scmi-agent@1 {
457 compatible = "sandbox,scmi-agent";
458 #address-cells = <1>;
459 #size-cells = <0>;
460
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200461 clk_scmi1: protocol@14 {
462 reg = <0x14>;
463 #clock-cells = <1>;
464 };
465
Etienne Carriere02fd1262020-09-09 18:44:00 +0200466 protocol@10 {
467 reg = <0x10>;
468 };
469 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700470 };
471
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100472 pinctrl-gpio {
473 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700474
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100475 gpio_a: base-gpios {
476 compatible = "sandbox,gpio";
477 gpio-controller;
478 #gpio-cells = <1>;
479 gpio-bank-name = "a";
480 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200481 hog_input_active_low {
482 gpio-hog;
483 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200484 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200485 };
486 hog_input_active_high {
487 gpio-hog;
488 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200489 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200490 };
491 hog_output_low {
492 gpio-hog;
493 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200494 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200495 };
496 hog_output_high {
497 gpio-hog;
498 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200499 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200500 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100501 };
502
503 gpio_b: extra-gpios {
504 compatible = "sandbox,gpio";
505 gpio-controller;
506 #gpio-cells = <5>;
507 gpio-bank-name = "b";
508 sandbox,gpio-count = <10>;
509 };
Simon Glass25348a42014-10-13 23:42:11 -0600510
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100511 gpio_c: pinmux-gpios {
512 compatible = "sandbox,gpio";
513 gpio-controller;
514 #gpio-cells = <2>;
515 gpio-bank-name = "c";
516 sandbox,gpio-count = <10>;
517 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100518 };
519
Simon Glass7df766e2014-12-10 08:55:55 -0700520 i2c@0 {
521 #address-cells = <1>;
522 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600523 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700524 compatible = "sandbox,i2c";
525 clock-frequency = <100000>;
526 eeprom@2c {
527 reg = <0x2c>;
528 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700529 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200530 partitions {
531 compatible = "fixed-partitions";
532 #address-cells = <1>;
533 #size-cells = <1>;
534 bootcount_i2c: bootcount@10 {
535 reg = <10 2>;
536 };
537 };
Simon Glass7df766e2014-12-10 08:55:55 -0700538 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200539
Simon Glass336b2952015-05-22 15:42:17 -0600540 rtc_0: rtc@43 {
541 reg = <0x43>;
542 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700543 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600544 };
545
546 rtc_1: rtc@61 {
547 reg = <0x61>;
548 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700549 sandbox,emul = <&emul1>;
550 };
551
552 i2c_emul: emul {
553 reg = <0xff>;
554 compatible = "sandbox,i2c-emul-parent";
555 emul_eeprom: emul-eeprom {
556 compatible = "sandbox,i2c-eeprom";
557 sandbox,filename = "i2c.bin";
558 sandbox,size = <256>;
559 };
560 emul0: emul0 {
561 compatible = "sandbox,i2c-rtc";
562 };
563 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600564 compatible = "sandbox,i2c-rtc";
565 };
566 };
567
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200568 sandbox_pmic: sandbox_pmic {
569 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700570 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200571 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200572
573 mc34708: pmic@41 {
574 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700575 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200576 };
Simon Glass7df766e2014-12-10 08:55:55 -0700577 };
578
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100579 bootcount@0 {
580 compatible = "u-boot,bootcount-rtc";
581 rtc = <&rtc_1>;
582 offset = <0x13>;
583 };
584
Michal Simek4f18f922020-05-28 11:48:55 +0200585 bootcount {
586 compatible = "u-boot,bootcount-i2c-eeprom";
587 i2c-eeprom = <&bootcount_i2c>;
588 };
589
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100590 adc@0 {
591 compatible = "sandbox,adc";
592 vdd-supply = <&buck2>;
593 vss-microvolts = <0>;
594 };
595
Simon Glass515dcff2020-02-06 09:55:00 -0700596 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700597 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700598 interrupt-controller;
599 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700600 };
601
Simon Glass90b6fef2016-01-18 19:52:26 -0700602 lcd {
603 u-boot,dm-pre-reloc;
604 compatible = "sandbox,lcd-sdl";
605 xres = <1366>;
606 yres = <768>;
607 };
608
Simon Glassd783eb32015-07-06 12:54:34 -0600609 leds {
610 compatible = "gpio-leds";
611
612 iracibble {
613 gpios = <&gpio_a 1 0>;
614 label = "sandbox:red";
615 };
616
617 martinet {
618 gpios = <&gpio_a 2 0>;
619 label = "sandbox:green";
620 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200621
622 default_on {
623 gpios = <&gpio_a 5 0>;
624 label = "sandbox:default_on";
625 default-state = "on";
626 };
627
628 default_off {
629 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400630 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200631 default-state = "off";
632 };
Simon Glassd783eb32015-07-06 12:54:34 -0600633 };
634
Stephen Warren62f2c902016-05-16 17:41:37 -0600635 mbox: mbox {
636 compatible = "sandbox,mbox";
637 #mbox-cells = <1>;
638 };
639
640 mbox-test {
641 compatible = "sandbox,mbox-test";
642 mboxes = <&mbox 100>, <&mbox 1>;
643 mbox-names = "other", "test";
644 };
645
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900646 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400647 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900648 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400649 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900650 compatible = "sandbox,cpu_sandbox";
651 u-boot,dm-pre-reloc;
652 };
Mario Sixdea5df72018-08-06 10:23:44 +0200653
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900654 cpu-test2 {
655 compatible = "sandbox,cpu_sandbox";
656 u-boot,dm-pre-reloc;
657 };
Mario Sixdea5df72018-08-06 10:23:44 +0200658
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900659 cpu-test3 {
660 compatible = "sandbox,cpu_sandbox";
661 u-boot,dm-pre-reloc;
662 };
Mario Sixdea5df72018-08-06 10:23:44 +0200663 };
664
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500665 chipid: chipid {
666 compatible = "sandbox,soc";
667 };
668
Simon Glassc953aaf2018-12-10 10:37:34 -0700669 i2s: i2s {
670 compatible = "sandbox,i2s";
671 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700672 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700673 };
674
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200675 nop-test_0 {
676 compatible = "sandbox,nop_sandbox1";
677 nop-test_1 {
678 compatible = "sandbox,nop_sandbox2";
679 bind = "True";
680 };
681 nop-test_2 {
682 compatible = "sandbox,nop_sandbox2";
683 bind = "False";
684 };
685 };
686
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200687 misc-test {
688 compatible = "sandbox,misc_sandbox";
689 };
690
Simon Glasse4fef742017-04-23 20:02:07 -0600691 mmc2 {
692 compatible = "sandbox,mmc";
693 };
694
695 mmc1 {
696 compatible = "sandbox,mmc";
697 };
698
699 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600700 compatible = "sandbox,mmc";
701 };
702
Simon Glass53a68b32019-02-16 20:24:50 -0700703 pch {
704 compatible = "sandbox,pch";
705 };
706
Tom Rini4a3ca482020-02-11 12:41:23 -0500707 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700708 compatible = "sandbox,pci";
709 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500710 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700711 #address-cells = <3>;
712 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600713 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700714 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700715 pci@0,0 {
716 compatible = "pci-generic";
717 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600718 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700719 };
Alex Margineanf1274432019-06-07 11:24:24 +0300720 pci@1,0 {
721 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600722 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
723 reg = <0x02000814 0 0 0 0
724 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600725 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300726 };
Simon Glass937bb472019-12-06 21:41:57 -0700727 p2sb-pci@2,0 {
728 compatible = "sandbox,p2sb";
729 reg = <0x02001010 0 0 0 0>;
730 sandbox,emul = <&p2sb_emul>;
731
732 adder {
733 intel,p2sb-port-id = <3>;
734 compatible = "sandbox,adder";
735 };
736 };
Simon Glass8c501022019-12-06 21:41:54 -0700737 pci@1e,0 {
738 compatible = "sandbox,pmc";
739 reg = <0xf000 0 0 0 0>;
740 sandbox,emul = <&pmc_emul1e>;
741 acpi-base = <0x400>;
742 gpe0-dwx-mask = <0xf>;
743 gpe0-dwx-shift-base = <4>;
744 gpe0-dw = <6 7 9>;
745 gpe0-sts = <0x20>;
746 gpe0-en = <0x30>;
747 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700748 pci@1f,0 {
749 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600750 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
751 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600752 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700753 };
754 };
755
Simon Glassb98ba4c2019-09-25 08:56:10 -0600756 pci-emul0 {
757 compatible = "sandbox,pci-emul-parent";
758 swap_case_emul0_0: emul0@0,0 {
759 compatible = "sandbox,swap-case";
760 };
761 swap_case_emul0_1: emul0@1,0 {
762 compatible = "sandbox,swap-case";
763 use-ea;
764 };
765 swap_case_emul0_1f: emul0@1f,0 {
766 compatible = "sandbox,swap-case";
767 };
Simon Glass937bb472019-12-06 21:41:57 -0700768 p2sb_emul: emul@2,0 {
769 compatible = "sandbox,p2sb-emul";
770 };
Simon Glass8c501022019-12-06 21:41:54 -0700771 pmc_emul1e: emul@1e,0 {
772 compatible = "sandbox,pmc-emul";
773 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600774 };
775
Tom Rini4a3ca482020-02-11 12:41:23 -0500776 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700777 compatible = "sandbox,pci";
778 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500779 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700780 #address-cells = <3>;
781 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700782 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
783 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
784 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700785 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200786 0x0c 0x00 0x1234 0x5678
787 0x10 0x00 0x1234 0x5678>;
788 pci@10,0 {
789 reg = <0x8000 0 0 0 0>;
790 };
Bin Meng408e5902018-08-03 01:14:41 -0700791 };
792
Tom Rini4a3ca482020-02-11 12:41:23 -0500793 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700794 compatible = "sandbox,pci";
795 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500796 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700797 #address-cells = <3>;
798 #size-cells = <2>;
799 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
800 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
801 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
802 pci@1f,0 {
803 compatible = "pci-generic";
804 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600805 sandbox,emul = <&swap_case_emul2_1f>;
806 };
807 };
808
809 pci-emul2 {
810 compatible = "sandbox,pci-emul-parent";
811 swap_case_emul2_1f: emul2@1f,0 {
812 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700813 };
814 };
815
Ramon Friedc64f19b2019-04-27 11:15:23 +0300816 pci_ep: pci_ep {
817 compatible = "sandbox,pci_ep";
818 };
819
Simon Glass9c433fe2017-04-23 20:10:44 -0600820 probing {
821 compatible = "simple-bus";
822 test1 {
823 compatible = "denx,u-boot-probe-test";
824 };
825
826 test2 {
827 compatible = "denx,u-boot-probe-test";
828 };
829
830 test3 {
831 compatible = "denx,u-boot-probe-test";
832 };
833
834 test4 {
835 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100836 first-syscon = <&syscon0>;
837 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100838 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600839 };
840 };
841
Stephen Warren92c67fa2016-07-13 13:45:31 -0600842 pwrdom: power-domain {
843 compatible = "sandbox,power-domain";
844 #power-domain-cells = <1>;
845 };
846
847 power-domain-test {
848 compatible = "sandbox,power-domain-test";
849 power-domains = <&pwrdom 2>;
850 };
851
Simon Glass5620cf82018-10-01 12:22:40 -0600852 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600853 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600854 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600855 };
856
857 pwm2 {
858 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600859 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600860 };
861
Simon Glass3d355e62015-07-06 12:54:31 -0600862 ram {
863 compatible = "sandbox,ram";
864 };
865
Simon Glassd860f222015-07-06 12:54:29 -0600866 reset@0 {
867 compatible = "sandbox,warm-reset";
868 };
869
870 reset@1 {
871 compatible = "sandbox,reset";
872 };
873
Stephen Warren6488e642016-06-17 09:43:59 -0600874 resetc: reset-ctl {
875 compatible = "sandbox,reset-ctl";
876 #reset-cells = <1>;
877 };
878
879 reset-ctl-test {
880 compatible = "sandbox,reset-ctl-test";
881 resets = <&resetc 100>, <&resetc 2>;
882 reset-names = "other", "test";
883 };
884
Sughosh Ganu23e37512019-12-28 23:58:31 +0530885 rng {
886 compatible = "sandbox,sandbox-rng";
887 };
888
Nishanth Menonedf85812015-09-17 15:42:41 -0500889 rproc_1: rproc@1 {
890 compatible = "sandbox,test-processor";
891 remoteproc-name = "remoteproc-test-dev1";
892 };
893
894 rproc_2: rproc@2 {
895 compatible = "sandbox,test-processor";
896 internal-memory-mapped;
897 remoteproc-name = "remoteproc-test-dev2";
898 };
899
Simon Glass5620cf82018-10-01 12:22:40 -0600900 panel {
901 compatible = "simple-panel";
902 backlight = <&backlight 0 100>;
903 };
904
Ramon Fried26ed32e2018-07-02 02:57:59 +0300905 smem@0 {
906 compatible = "sandbox,smem";
907 };
908
Simon Glass76072ac2018-12-10 10:37:36 -0700909 sound {
910 compatible = "sandbox,sound";
911 cpu {
912 sound-dai = <&i2s 0>;
913 };
914
915 codec {
916 sound-dai = <&audio 0>;
917 };
918 };
919
Simon Glass25348a42014-10-13 23:42:11 -0600920 spi@0 {
921 #address-cells = <1>;
922 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600923 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600924 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +0200925 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass25348a42014-10-13 23:42:11 -0600926 spi.bin@0 {
927 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000928 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600929 spi-max-frequency = <40000000>;
930 sandbox,filename = "spi.bin";
931 };
Ovidiu Panaitae734732020-12-14 19:06:47 +0200932 spi.bin@1 {
933 reg = <1>;
934 compatible = "spansion,m25p16", "jedec,spi-nor";
935 spi-max-frequency = <50000000>;
936 sandbox,filename = "spi.bin";
937 spi-cpol;
938 spi-cpha;
939 };
Simon Glass25348a42014-10-13 23:42:11 -0600940 };
941
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100942 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600943 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200944 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600945 };
946
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100947 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600948 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600949 reg = <0x20 5
950 0x28 6
951 0x30 7
952 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600953 };
954
Patrick Delaunayee010432019-03-07 09:57:13 +0100955 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900956 compatible = "simple-mfd", "syscon";
957 reg = <0x40 5
958 0x48 6
959 0x50 7
960 0x58 8>;
961 };
962
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530963 syscon3: syscon@3 {
964 compatible = "simple-mfd", "syscon";
965 reg = <0x000100 0x10>;
966
967 muxcontroller0: a-mux-controller {
968 compatible = "mmio-mux";
969 #mux-control-cells = <1>;
970
971 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
972 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
973 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
974 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
975 u-boot,mux-autoprobe;
976 };
977 };
978
979 muxcontroller1: emul-mux-controller {
980 compatible = "mux-emul";
981 #mux-control-cells = <0>;
982 u-boot,mux-autoprobe;
983 idle-state = <0xabcd>;
984 };
985
Simon Glass791a17f2020-12-16 21:20:27 -0700986 testfdtm0 {
987 compatible = "denx,u-boot-fdtm-test";
988 };
989
990 testfdtm1: testfdtm1 {
991 compatible = "denx,u-boot-fdtm-test";
992 };
993
994 testfdtm2 {
995 compatible = "denx,u-boot-fdtm-test";
996 };
997
Sean Anderson79d3bba2020-09-28 10:52:23 -0400998 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800999 compatible = "sandbox,timer";
1000 clock-frequency = <1000000>;
1001 };
1002
Sean Anderson79d3bba2020-09-28 10:52:23 -04001003 timer@1 {
1004 compatible = "sandbox,timer";
1005 sandbox,timebase-frequency-fallback;
1006 };
1007
Miquel Raynal80938c12018-05-15 11:57:27 +02001008 tpm2 {
1009 compatible = "sandbox,tpm2";
1010 };
1011
Simon Glass5b968632015-05-22 15:42:15 -06001012 uart0: serial {
1013 compatible = "sandbox,serial";
1014 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -05001015 };
1016
Simon Glass31680482015-03-25 12:23:05 -06001017 usb_0: usb@0 {
1018 compatible = "sandbox,usb";
1019 status = "disabled";
1020 hub {
1021 compatible = "sandbox,usb-hub";
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1024 flash-stick {
1025 reg = <0>;
1026 compatible = "sandbox,usb-flash";
1027 };
1028 };
1029 };
1030
1031 usb_1: usb@1 {
1032 compatible = "sandbox,usb";
1033 hub {
1034 compatible = "usb-hub";
1035 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001036 #address-cells = <1>;
1037 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001038 hub-emul {
1039 compatible = "sandbox,usb-hub";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001042 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001043 reg = <0>;
1044 compatible = "sandbox,usb-flash";
1045 sandbox,filepath = "testflash.bin";
1046 };
1047
Simon Glass4700fe52015-11-08 23:48:01 -07001048 flash-stick@1 {
1049 reg = <1>;
1050 compatible = "sandbox,usb-flash";
1051 sandbox,filepath = "testflash1.bin";
1052 };
1053
1054 flash-stick@2 {
1055 reg = <2>;
1056 compatible = "sandbox,usb-flash";
1057 sandbox,filepath = "testflash2.bin";
1058 };
1059
Simon Glassc0ccc722015-11-08 23:48:08 -07001060 keyb@3 {
1061 reg = <3>;
1062 compatible = "sandbox,usb-keyb";
1063 };
1064
Simon Glass31680482015-03-25 12:23:05 -06001065 };
Michael Walle7c961322020-06-02 01:47:07 +02001066
1067 usbstor@1 {
1068 reg = <1>;
1069 };
1070 usbstor@3 {
1071 reg = <3>;
1072 };
Simon Glass31680482015-03-25 12:23:05 -06001073 };
1074 };
1075
1076 usb_2: usb@2 {
1077 compatible = "sandbox,usb";
1078 status = "disabled";
1079 };
1080
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001081 spmi: spmi@0 {
1082 compatible = "sandbox,spmi";
1083 #address-cells = <0x1>;
1084 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001085 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001086 pm8916@0 {
1087 compatible = "qcom,spmi-pmic";
1088 reg = <0x0 0x1>;
1089 #address-cells = <0x1>;
1090 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001091 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001092
1093 spmi_gpios: gpios@c000 {
1094 compatible = "qcom,pm8916-gpio";
1095 reg = <0xc000 0x400>;
1096 gpio-controller;
1097 gpio-count = <4>;
1098 #gpio-cells = <2>;
1099 gpio-bank-name="spmi";
1100 };
1101 };
1102 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001103
1104 wdt0: wdt@0 {
1105 compatible = "sandbox,wdt";
1106 };
Rob Clarka471b672018-01-10 11:33:30 +01001107
Mario Six95922152018-08-09 14:51:19 +02001108 axi: axi@0 {
1109 compatible = "sandbox,axi";
1110 #address-cells = <0x1>;
1111 #size-cells = <0x1>;
1112 store@0 {
1113 compatible = "sandbox,sandbox_store";
1114 reg = <0x0 0x400>;
1115 };
1116 };
1117
Rob Clarka471b672018-01-10 11:33:30 +01001118 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001119 #address-cells = <1>;
1120 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001121 setting = "sunrise ohoka";
1122 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001123 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001124 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001125 chosen-test {
1126 compatible = "denx,u-boot-fdt-test";
1127 reg = <9 1>;
1128 };
1129 };
Mario Six35616ef2018-03-12 14:53:33 +01001130
1131 translation-test@8000 {
1132 compatible = "simple-bus";
1133 reg = <0x8000 0x4000>;
1134
1135 #address-cells = <0x2>;
1136 #size-cells = <0x1>;
1137
1138 ranges = <0 0x0 0x8000 0x1000
1139 1 0x100 0x9000 0x1000
1140 2 0x200 0xA000 0x1000
1141 3 0x300 0xB000 0x1000
Dario Binacchib574d682020-12-30 00:16:21 +01001142 4 0x400 0xC000 0x1000
Mario Six35616ef2018-03-12 14:53:33 +01001143 >;
1144
Fabien Dessenne22236e02019-05-31 15:11:30 +02001145 dma-ranges = <0 0x000 0x10000000 0x1000
1146 1 0x100 0x20000000 0x1000
1147 >;
1148
Mario Six35616ef2018-03-12 14:53:33 +01001149 dev@0,0 {
1150 compatible = "denx,u-boot-fdt-dummy";
1151 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001152 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001153 };
1154
1155 dev@1,100 {
1156 compatible = "denx,u-boot-fdt-dummy";
1157 reg = <1 0x100 0x1000>;
1158
1159 };
1160
1161 dev@2,200 {
1162 compatible = "denx,u-boot-fdt-dummy";
1163 reg = <2 0x200 0x1000>;
1164 };
1165
1166
1167 noxlatebus@3,300 {
1168 compatible = "simple-bus";
1169 reg = <3 0x300 0x1000>;
1170
1171 #address-cells = <0x1>;
1172 #size-cells = <0x0>;
1173
1174 dev@42 {
1175 compatible = "denx,u-boot-fdt-dummy";
1176 reg = <0x42>;
1177 };
1178 };
Dario Binacchib574d682020-12-30 00:16:21 +01001179
1180 xlatebus@4,400 {
1181 compatible = "sandbox,zero-size-cells-bus";
1182 reg = <4 0x400 0x1000>;
1183 #address-cells = <1>;
1184 #size-cells = <1>;
1185 ranges = <0 4 0x400 0x1000>;
1186
1187 devs {
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1190
1191 dev@19 {
1192 compatible = "denx,u-boot-fdt-dummy";
1193 reg = <0x19>;
1194 };
1195 };
1196 };
1197
Mario Six35616ef2018-03-12 14:53:33 +01001198 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001199
1200 osd {
1201 compatible = "sandbox,sandbox_osd";
1202 };
Tom Rinib93eea72018-09-30 18:16:51 -04001203
Jens Wiklander86afaa62018-09-25 16:40:16 +02001204 sandbox_tee {
1205 compatible = "sandbox,tee";
1206 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001207
1208 sandbox_virtio1 {
1209 compatible = "sandbox,virtio1";
1210 };
1211
1212 sandbox_virtio2 {
1213 compatible = "sandbox,virtio2";
1214 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001215
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001216 sandbox_scmi {
1217 compatible = "sandbox,scmi-devices";
1218 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001219 resets = <&reset_scmi0 3>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001220 };
1221
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001222 pinctrl {
1223 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001224
Sean Anderson3438e3b2020-09-14 11:01:57 -04001225 pinctrl-names = "default", "alternate";
1226 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1227 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001228
Sean Anderson3438e3b2020-09-14 11:01:57 -04001229 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001230 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001231 pins = "P5";
1232 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001233 bias-pull-up;
1234 input-disable;
1235 };
1236 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001237 pins = "P6";
1238 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001239 output-high;
1240 drive-open-drain;
1241 };
1242 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001243 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001244 bias-pull-down;
1245 input-enable;
1246 };
1247 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001248 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001249 bias-disable;
1250 };
1251 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001252
1253 pinctrl_i2c: i2c {
1254 groups {
1255 groups = "I2C_UART";
1256 function = "I2C";
1257 };
1258
1259 pins {
1260 pins = "P0", "P1";
1261 drive-open-drain;
1262 };
1263 };
1264
1265 pinctrl_i2s: i2s {
1266 groups = "SPI_I2S";
1267 function = "I2S";
1268 };
1269
1270 pinctrl_spi: spi {
1271 groups = "SPI_I2S";
1272 function = "SPI";
1273
1274 cs {
1275 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1276 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1277 };
1278 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001279 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001280
1281 hwspinlock@0 {
1282 compatible = "sandbox,hwspinlock";
1283 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001284
1285 dma: dma {
1286 compatible = "sandbox,dma";
1287 #dma-cells = <1>;
1288
1289 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1290 dma-names = "m2m", "tx0", "rx0";
1291 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001292
Alex Marginean0649be52019-07-12 10:13:53 +03001293 /*
1294 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1295 * end of the test. If parent mdio is removed first, clean-up of the
1296 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1297 * active at the end of the test. That it turn doesn't allow the mdio
1298 * class to be destroyed, triggering an error.
1299 */
1300 mdio-mux-test {
1301 compatible = "sandbox,mdio-mux";
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1304 mdio-parent-bus = <&mdio>;
1305
1306 mdio-ch-test@0 {
1307 reg = <0>;
1308 };
1309 mdio-ch-test@1 {
1310 reg = <1>;
1311 };
1312 };
1313
1314 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001315 compatible = "sandbox,mdio";
1316 };
Sean Andersonb7860542020-06-24 06:41:12 -04001317
1318 pm-bus-test {
1319 compatible = "simple-pm-bus";
1320 clocks = <&clk_sandbox 4>;
1321 power-domains = <&pwrdom 1>;
1322 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001323
1324 resetc2: syscon-reset {
1325 compatible = "syscon-reset";
1326 #reset-cells = <1>;
1327 regmap = <&syscon0>;
1328 offset = <1>;
1329 mask = <0x27FFFFFF>;
1330 assert-high = <0>;
1331 };
1332
1333 syscon-reset-test {
1334 compatible = "sandbox,misc_sandbox";
1335 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1336 reset-names = "valid", "no_mask", "out_of_range";
1337 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301338
Simon Glass458b66a2020-11-05 06:32:05 -07001339 sysinfo {
1340 compatible = "sandbox,sysinfo-sandbox";
1341 };
1342
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301343 some_regmapped-bus {
1344 #address-cells = <0x1>;
1345 #size-cells = <0x1>;
1346
1347 ranges = <0x0 0x0 0x10>;
1348 compatible = "simple-bus";
1349
1350 regmap-test_0 {
1351 reg = <0 0x10>;
1352 compatible = "sandbox,regmap_test";
1353 };
1354 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001355};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001356
1357#include "sandbox_pmic.dtsi"