Heiko Schocher | acb4f4a | 2006-12-21 16:14:48 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2003-2004 |
| 6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 7 | * |
| 8 | * (C) Copyright 2004 |
| 9 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
| 10 | * |
| 11 | * (C) Copyright 2004 |
| 12 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
| 13 | * |
| 14 | * See file CREDITS for list of people who contributed to this |
| 15 | * project. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or |
| 18 | * modify it under the terms of the GNU General Public License as |
| 19 | * published by the Free Software Foundation; either version 2 of |
| 20 | * the License, or (at your option) any later version. |
| 21 | * |
| 22 | * This program is distributed in the hope that it will be useful, |
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 25 | * GNU General Public License for more details. |
| 26 | * |
| 27 | * You should have received a copy of the GNU General Public License |
| 28 | * along with this program; if not, write to the Free Software |
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 30 | * MA 02111-1307 USA |
| 31 | */ |
| 32 | |
| 33 | #include <common.h> |
| 34 | #include <mpc5xxx.h> |
| 35 | #include <pci.h> |
| 36 | #include <malloc.h> |
| 37 | |
| 38 | /* some SIMPLE GPIO Pins */ |
| 39 | #define GPIO_USB_8 (31-12) |
| 40 | #define GPIO_USB_7 (31-13) |
| 41 | #define GPIO_USB_6 (31-14) |
| 42 | #define GPIO_USB_0 (31-15) |
| 43 | #define GPIO_PSC3_7 (31-18) |
| 44 | #define GPIO_PSC3_6 (31-19) |
| 45 | #define GPIO_PSC3_1 (31-22) |
| 46 | #define GPIO_PSC3_0 (31-23) |
| 47 | |
| 48 | /* some simple Interrupt GPIO Pins */ |
| 49 | #define GPIO_PSC3_8 2 |
| 50 | #define GPIO_USB1_9 3 |
| 51 | |
| 52 | #define GPT_OUT_0 0x00000027 |
| 53 | #define GPT_OUT_1 0x00000037 |
| 54 | #define GPT_DISABLE 0x00000000 /* GPT pin disabled */ |
| 55 | |
| 56 | #define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \ |
| 57 | pgpio->simple_ddr |= (1 << n); \ |
| 58 | pgpio->simple_gpioe |= (1 << n); \ |
| 59 | } |
| 60 | |
| 61 | #define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \ |
| 62 | pgpio->simple_gpioe |= (1 << n); \ |
| 63 | } |
| 64 | |
| 65 | #define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \ |
| 66 | (pgpio->simple_dvo | (1 << n)) : \ |
| 67 | (pgpio->simple_dvo & ~(1 << n)) ) |
| 68 | |
| 69 | #define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1) |
| 70 | #define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1) |
| 71 | |
| 72 | |
| 73 | |
| 74 | #define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \ |
| 75 | (pgpio->sint_dvo | (1 << n)) : \ |
| 76 | (pgpio->sint_dvo & ~(1 << n)) ) |
| 77 | |
| 78 | #define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \ |
| 79 | pgpio->sint_ddr |= (1 << n); \ |
| 80 | GP_SINT_SET_O(n, v); \ |
| 81 | pgpio->sint_gpioe |= (1 << n); \ |
| 82 | } |
| 83 | |
| 84 | #define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \ |
| 85 | pgpio->sint_gpioe |= (1 << n); \ |
| 86 | } |
| 87 | |
| 88 | #define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1) |
| 89 | #define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1) |
| 90 | |
| 91 | #define GP_TIMER_ENABLE_O(n, v) ( \ |
| 92 | ((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \ |
| 93 | GPT_OUT_1 : \ |
| 94 | GPT_OUT_0 ) |
| 95 | |
| 96 | #define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v) |
| 97 | |
| 98 | #define GP_TIMER_GET_O(n, v) ( \ |
| 99 | (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4) |
| 100 | |
| 101 | #define GP_TIMER_GET_I(n, v) ( \ |
| 102 | (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8) |
| 103 | |
| 104 | #ifndef CFG_RAMBOOT |
| 105 | static void sdram_start (int hi_addr) |
| 106 | { |
| 107 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
| 108 | |
| 109 | /* unlock mode register */ |
| 110 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
| 111 | __asm__ volatile ("sync"); |
| 112 | |
| 113 | /* precharge all banks */ |
| 114 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
| 115 | __asm__ volatile ("sync"); |
| 116 | |
| 117 | #if SDRAM_DDR |
| 118 | /* set mode register: extended mode */ |
| 119 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
| 120 | __asm__ volatile ("sync"); |
| 121 | |
| 122 | /* set mode register: reset DLL */ |
| 123 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
| 124 | __asm__ volatile ("sync"); |
| 125 | #endif |
| 126 | |
| 127 | /* precharge all banks */ |
| 128 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
| 129 | __asm__ volatile ("sync"); |
| 130 | |
| 131 | /* auto refresh */ |
| 132 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
| 133 | __asm__ volatile ("sync"); |
| 134 | |
| 135 | /* set mode register */ |
| 136 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
| 137 | __asm__ volatile ("sync"); |
| 138 | |
| 139 | /* normal operation */ |
| 140 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
| 141 | __asm__ volatile ("sync"); |
| 142 | } |
| 143 | #endif |
| 144 | |
| 145 | /* |
| 146 | * ATTENTION: Although partially referenced initdram does NOT make real use |
| 147 | * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
| 148 | * is something else than 0x00000000. |
| 149 | */ |
| 150 | |
| 151 | long int initdram (int board_type) |
| 152 | { |
| 153 | ulong dramsize = 0; |
| 154 | #ifndef CFG_RAMBOOT |
| 155 | ulong test1, test2; |
| 156 | |
| 157 | /* setup SDRAM chip selects */ |
| 158 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ |
| 159 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ |
| 160 | __asm__ volatile ("sync"); |
| 161 | |
| 162 | /* setup config registers */ |
| 163 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
| 164 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
| 165 | __asm__ volatile ("sync"); |
| 166 | |
| 167 | #if SDRAM_DDR |
| 168 | /* set tap delay */ |
| 169 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
| 170 | __asm__ volatile ("sync"); |
| 171 | #endif |
| 172 | |
| 173 | /* find RAM size using SDRAM CS0 only */ |
| 174 | sdram_start(0); |
| 175 | test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); |
| 176 | sdram_start(1); |
| 177 | test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); |
| 178 | if (test1 > test2) { |
| 179 | sdram_start(0); |
| 180 | dramsize = test1; |
| 181 | } else { |
| 182 | dramsize = test2; |
| 183 | } |
| 184 | |
| 185 | /* memory smaller than 1MB is impossible */ |
| 186 | if (dramsize < (1 << 20)) { |
| 187 | dramsize = 0; |
| 188 | } |
| 189 | |
| 190 | /* set SDRAM CS0 size according to the amount of RAM found */ |
| 191 | if (dramsize > 0) { |
| 192 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + |
| 193 | __builtin_ffs(dramsize >> 20) - 1; |
| 194 | } else { |
| 195 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
| 196 | } |
| 197 | |
| 198 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
| 199 | #else /* CFG_RAMBOOT */ |
| 200 | |
| 201 | /* retrieve size of memory connected to SDRAM CS0 */ |
| 202 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
| 203 | if (dramsize >= 0x13) { |
| 204 | dramsize = (1 << (dramsize - 0x13)) << 20; |
| 205 | } else { |
| 206 | dramsize = 0; |
| 207 | } |
| 208 | |
| 209 | /* retrieve size of memory connected to SDRAM CS1 */ |
| 210 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
| 211 | if (dramsize2 >= 0x13) { |
| 212 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
| 213 | } else { |
| 214 | dramsize2 = 0; |
| 215 | } |
| 216 | |
| 217 | #endif /* CFG_RAMBOOT */ |
| 218 | |
| 219 | /* return dramsize + dramsize2; */ |
| 220 | return dramsize; |
| 221 | } |
| 222 | |
| 223 | int checkboard (void) |
| 224 | { |
| 225 | puts ("Board: MAN UC101\n"); |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | static void init_ports (void) |
| 230 | { |
| 231 | volatile struct mpc5xxx_gpio *pgpio = |
| 232 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; |
| 233 | |
| 234 | GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */ |
| 235 | GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */ |
| 236 | GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */ |
| 237 | GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */ |
| 238 | GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */ |
| 239 | GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */ |
| 240 | GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */ |
| 241 | GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */ |
| 242 | GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */ |
| 243 | GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */ |
| 244 | GP_TIMER_ENABLE_O(4, 0); /* LED H4 */ |
| 245 | GP_TIMER_ENABLE_O(5, 0); /* LED H5 */ |
| 246 | GP_TIMER_ENABLE_O(3, 0); /* LED HB */ |
| 247 | GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */ |
| 248 | } |
| 249 | |
| 250 | #ifdef CONFIG_PREBOOT |
| 251 | |
| 252 | static uchar kbd_magic_prefix[] = "key_magic"; |
| 253 | static uchar kbd_command_prefix[] = "key_cmd"; |
| 254 | |
| 255 | struct kbd_data_t { |
| 256 | char s1; |
| 257 | }; |
| 258 | |
| 259 | struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) |
| 260 | { |
| 261 | volatile struct mpc5xxx_gpio *pgpio = |
| 262 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; |
| 263 | |
| 264 | kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \ |
| 265 | GP_SIMP_GET_I(GPIO_USB_7) << 2 | \ |
| 266 | GP_SIMP_GET_I(GPIO_USB_6) << 1 | \ |
| 267 | GP_SIMP_GET_I(GPIO_USB_0) << 0; |
| 268 | return kbd_data; |
| 269 | } |
| 270 | |
| 271 | static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str) |
| 272 | { |
| 273 | char s1 = str[0]; |
| 274 | |
| 275 | if (s1 >= '0' && s1 <= '9') |
| 276 | s1 -= '0'; |
| 277 | else if (s1 >= 'a' && s1 <= 'f') |
| 278 | s1 = s1 - 'a' + 10; |
| 279 | else if (s1 >= 'A' && s1 <= 'F') |
| 280 | s1 = s1 - 'A' + 10; |
| 281 | else |
| 282 | return -1; |
| 283 | |
| 284 | if (s1 != kbd_data->s1) return -1; |
| 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | static uchar *key_match (const struct kbd_data_t *kbd_data) |
| 289 | { |
| 290 | uchar magic[sizeof (kbd_magic_prefix) + 1]; |
| 291 | uchar *suffix; |
| 292 | uchar *kbd_magic_keys; |
| 293 | |
| 294 | /* |
| 295 | * The following string defines the characters that can be appended |
| 296 | * to "key_magic" to form the names of environment variables that |
| 297 | * hold "magic" key codes, i. e. such key codes that can cause |
| 298 | * pre-boot actions. If the string is empty (""), then only |
| 299 | * "key_magic" is checked (old behaviour); the string "125" causes |
| 300 | * checks for "key_magic1", "key_magic2" and "key_magic5", etc. |
| 301 | */ |
| 302 | if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) |
| 303 | kbd_magic_keys = ""; |
| 304 | |
| 305 | /* loop over all magic keys; |
| 306 | * use '\0' suffix in case of empty string |
| 307 | */ |
| 308 | for (suffix = kbd_magic_keys; *suffix || |
| 309 | suffix == kbd_magic_keys; ++suffix) { |
| 310 | sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); |
| 311 | |
| 312 | if (compare_magic(kbd_data, getenv(magic)) == 0) { |
| 313 | uchar cmd_name[sizeof (kbd_command_prefix) + 1]; |
| 314 | char *cmd; |
| 315 | |
| 316 | sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); |
| 317 | cmd = getenv (cmd_name); |
| 318 | |
| 319 | return (cmd); |
| 320 | } |
| 321 | } |
| 322 | |
| 323 | return (NULL); |
| 324 | } |
| 325 | |
| 326 | #endif /* CONFIG_PREBOOT */ |
| 327 | |
| 328 | int misc_init_r (void) |
| 329 | { |
| 330 | /* Init the I/O ports */ |
| 331 | init_ports (); |
| 332 | |
| 333 | #ifdef CONFIG_PREBOOT |
| 334 | struct kbd_data_t kbd_data; |
| 335 | /* Decode keys */ |
| 336 | uchar *str = strdup (key_match (get_keys (&kbd_data))); |
| 337 | /* Set or delete definition */ |
| 338 | setenv ("preboot", str); |
| 339 | free (str); |
| 340 | #endif /* CONFIG_PREBOOT */ |
| 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | int board_early_init_r (void) |
| 345 | { |
| 346 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
| 347 | *(vu_long *)MPC5XXX_BOOTCS_START = |
| 348 | *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); |
| 349 | *(vu_long *)MPC5XXX_BOOTCS_STOP = |
| 350 | *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); |
| 351 | /* Interbus enable it here ?? */ |
| 352 | *(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1; |
| 353 | return 0; |
| 354 | } |
| 355 | #ifdef CONFIG_PCI |
| 356 | static struct pci_controller hose; |
| 357 | |
| 358 | extern void pci_mpc5xxx_init(struct pci_controller *); |
| 359 | |
| 360 | void pci_init_board(void) |
| 361 | { |
| 362 | pci_mpc5xxx_init(&hose); |
| 363 | } |
| 364 | #endif |
| 365 | |
| 366 | #if defined(CONFIG_HW_WATCHDOG) |
| 367 | void hw_watchdog_reset(void) |
| 368 | { |
| 369 | /* Trigger HW Watchdog with TIMER_0 */ |
| 370 | *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1; |
| 371 | *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0; |
| 372 | } |
| 373 | #endif |
| 374 | |