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Enric Balletbò i Serra458d6032013-12-06 21:30:23 +01001/*
2 * ti_omap3_common.h
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * For more details, please see the technical documents listed at
9 * http://www.ti.com/product/omap3530
10 * http://www.ti.com/product/omap3630
11 * http://www.ti.com/product/dm3730
12 */
13
14#ifndef __CONFIG_TI_OMAP3_COMMON_H__
15#define __CONFIG_TI_OMAP3_COMMON_H__
16
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +010017/*
18 * High Level Configuration Options
19 */
20
21#define CONFIG_SYS_CACHELINE_SIZE 64
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010022
23#include <asm/arch/cpu.h>
Nishanth Menonfa96c962015-03-09 17:12:04 -050024#include <asm/arch/omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010025
Nishanth Menon3e46e3e2015-03-09 17:12:08 -050026/* Common ARM Erratas */
27#define CONFIG_ARM_ERRATA_454179
28#define CONFIG_ARM_ERRATA_430973
29#define CONFIG_ARM_ERRATA_621766
30
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010031/* The chip has SDRC controller */
32#define CONFIG_SDRC
33
34/* Clock Defines */
35#define V_OSCK 26000000 /* Clock output from T2 */
36#define V_SCLK (V_OSCK >> 1)
37
38/* NS16550 Configuration */
39#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
Thomas Chou52ac4432015-11-19 21:48:12 +080040#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Simon Glassbc0f4ea2014-10-22 21:37:15 -060041#ifdef CONFIG_SPL_BUILD
42# define CONFIG_SYS_NS16550_SERIAL
43# define CONFIG_SYS_NS16550_REG_SIZE (-4)
Simon Glassbc0f4ea2014-10-22 21:37:15 -060044#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010045#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
46 115200}
47
48/* Select serial console configuration */
49#define CONFIG_CONS_INDEX 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -060050#ifdef CONFIG_SPL_BUILD
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010051#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
52#define CONFIG_SERIAL3 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -060053#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010054
55/* Physical Memory Map */
56#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
57#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
58
59/*
60 * OMAP3 has 12 GP timers, they can be driven by the system clock
61 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
62 * This rate is divided by a local divisor.
63 */
64#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
65
66#define CONFIG_SYS_MONITOR_LEN (256 << 10)
67
68/* TWL4030 */
Igor Grinberg48b034a2015-10-08 21:12:25 +030069#define CONFIG_TWL4030_POWER
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010070
71/* SPL */
72#define CONFIG_SPL_TEXT_BASE 0x40200800
73#define CONFIG_SPL_MAX_SIZE (54 * 1024)
74#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
75#define CONFIG_SPL_POWER_SUPPORT
Tom Rinid9f808d2014-04-03 07:52:53 -040076#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
77 (64 << 20))
78
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010079#ifdef CONFIG_NAND
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010080#define CONFIG_SPL_NAND_SIMPLE
Tom Rinie10247f2014-04-03 15:17:15 -040081#define CONFIG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010082#endif
83
84/* Now bring in the rest of the common code. */
Nishanth Menonad63dd72015-07-22 18:05:41 -050085#include <configs/ti_armv7_omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010086
87#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */