blob: 07da58971904393e0babb03c1d7c9c8b189385ac [file] [log] [blame]
developerff9f2d42022-09-09 19:59:11 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
developer87bf1bc2023-07-19 17:15:41 +08007#include <fdtdec.h>
developerff9f2d42022-09-09 19:59:11 +08008#include <init.h>
9#include <asm/armv8/mmu.h>
10#include <asm/system.h>
11#include <asm/global_data.h>
Tom Rini5ba346a2022-10-28 20:27:08 -040012#include <linux/sizes.h>
developerff9f2d42022-09-09 19:59:11 +080013
14DECLARE_GLOBAL_DATA_PTR;
15
16int dram_init(void)
17{
developer87bf1bc2023-07-19 17:15:41 +080018 int ret;
19
20 ret = fdtdec_setup_mem_size_base();
21 if (ret)
22 return ret;
23
24 gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
developerff9f2d42022-09-09 19:59:11 +080025
26 return 0;
27}
28
Tom Rinie3b32642023-03-09 11:22:07 -050029void reset_cpu(void)
developerff9f2d42022-09-09 19:59:11 +080030{
31 psci_system_reset();
32}
33
34static struct mm_region mt7981_mem_map[] = {
35 {
36 /* DDR */
37 .virt = 0x40000000UL,
38 .phys = 0x40000000UL,
39 .size = 0x80000000UL,
40 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
41 }, {
42 .virt = 0x00000000UL,
43 .phys = 0x00000000UL,
44 .size = 0x40000000UL,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 }, {
49 0,
50 }
51};
52
53struct mm_region *mem_map = mt7981_mem_map;