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git01.mediatek.com / filogic / uboot / 844493d7e99cb795f3e28130ee09ba7a6441162f / . / src / arm / microchip / sam9x60.dtsi
blob: 36944e18a329ab44624b84d8ee9e42c3d1b70c04 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
4 *
5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
8 */
9
10#include <dt-bindings/dma/at91.h>
11#include <dt-bindings/pinctrl/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/clock/at91.h>
15#include <dt-bindings/mfd/at91-usart.h>
16#include <dt-bindings/mfd/atmel-flexcom.h>
17
18/ {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 model = "Microchip SAM9X60 SoC";
22 compatible = "microchip,sam9x60";
23 interrupt-parent = <&aic>;
24
25 aliases {
26 serial0 = &dbgu;
27 gpio0 = &pioA;
28 gpio1 = &pioB;
29 gpio2 = &pioC;
30 gpio3 = &pioD;
31 tcb0 = &tcb0;
32 tcb1 = &tcb1;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 compatible = "arm,arm926ej-s";
41 device_type = "cpu";
42 reg = <0>;
43 };
44 };
45
46 memory@20000000 {
47 device_type = "memory";
48 reg = <0x20000000 0x10000000>;
49 };
50
51 clocks {
52 slow_xtal: slow_xtal {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 };
56
57 main_xtal: main_xtal {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 };
61 };
62
63 sram: sram@300000 {
64 compatible = "mmio-sram";
65 reg = <0x00300000 0x100000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x00300000 0x100000>;
69 };
70
71 ahb {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 usb0: gadget@500000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "microchip,sam9x60-udc";
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
83 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
84 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
85 clock-names = "pclk", "hclk";
86 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
87 assigned-clock-rates = <480000000>;
88 status = "disabled";
89 };
90
91 usb1: ohci@600000 {
92 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
93 reg = <0x00600000 0x100000>;
94 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
95 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
96 clock-names = "ohci_clk", "hclk", "uhpck";
97 status = "disabled";
98 };
99
100 usb2: ehci@700000 {
101 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
102 reg = <0x00700000 0x100000>;
103 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
104 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
105 clock-names = "usb_clk", "ehci_clk";
106 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
107 assigned-clock-rates = <480000000>;
108 status = "disabled";
109 };
110
111 ebi: ebi@10000000 {
112 compatible = "microchip,sam9x60-ebi";
113 #address-cells = <2>;
114 #size-cells = <1>;
115 atmel,smc = <&smc>;
116 microchip,sfr = <&sfr>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
124 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
125 status = "disabled";
126
127 nand_controller: nand-controller {
128 compatible = "microchip,sam9x60-nand-controller";
129 ecc-engine = <&pmecc>;
130 #address-cells = <2>;
131 #size-cells = <1>;
132 ranges;
133 status = "disabled";
134 };
135 };
136
137 sdmmc0: sdio-host@80000000 {
138 compatible = "microchip,sam9x60-sdhci";
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
141 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
142 clock-names = "hclock", "multclk";
143 assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
144 assigned-clock-rates = <100000000>;
145 status = "disabled";
146 };
147
148 sdmmc1: sdio-host@90000000 {
149 compatible = "microchip,sam9x60-sdhci";
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
152 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
153 clock-names = "hclock", "multclk";
154 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
155 assigned-clock-rates = <100000000>;
156 status = "disabled";
157 };
158
159 apb {
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164
165 flx4: flexcom@f0000000 {
166 compatible = "atmel,sama5d2-flexcom";
167 reg = <0xf0000000 0x200>;
168 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0xf0000000 0x800>;
172 status = "disabled";
173
174 uart4: serial@200 {
175 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
176 reg = <0x200 0x200>;
177 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
178 dmas = <&dma0
179 (AT91_XDMAC_DT_MEM_IF(0) |
180 AT91_XDMAC_DT_PER_IF(1) |
181 AT91_XDMAC_DT_PERID(8))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]182 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]183 (AT91_XDMAC_DT_MEM_IF(0) |
184 AT91_XDMAC_DT_PER_IF(1) |
185 AT91_XDMAC_DT_PERID(9))>;
186 dma-names = "tx", "rx";
187 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
188 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]189 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]190 atmel,use-dma-rx;
191 atmel,use-dma-tx;
192 atmel,fifo-size = <16>;
193 status = "disabled";
194 };
195
196 spi4: spi@400 {
197 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
198 reg = <0x400 0x200>;
199 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
200 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
201 clock-names = "spi_clk";
202 dmas = <&dma0
203 (AT91_XDMAC_DT_MEM_IF(0) |
204 AT91_XDMAC_DT_PER_IF(1) |
205 AT91_XDMAC_DT_PERID(8))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]206 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]207 (AT91_XDMAC_DT_MEM_IF(0) |
208 AT91_XDMAC_DT_PER_IF(1) |
209 AT91_XDMAC_DT_PERID(9))>;
210 dma-names = "tx", "rx";
211 atmel,fifo-size = <16>;
212 status = "disabled";
213 };
214
215 i2c4: i2c@600 {
216 compatible = "microchip,sam9x60-i2c";
217 reg = <0x600 0x200>;
218 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]219 #address-cells = <1>;
220 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]221 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
222 dmas = <&dma0
223 (AT91_XDMAC_DT_MEM_IF(0) |
224 AT91_XDMAC_DT_PER_IF(1) |
225 AT91_XDMAC_DT_PERID(8))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]226 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]227 (AT91_XDMAC_DT_MEM_IF(0) |
228 AT91_XDMAC_DT_PER_IF(1) |
229 AT91_XDMAC_DT_PERID(9))>;
230 dma-names = "tx", "rx";
231 atmel,fifo-size = <16>;
232 status = "disabled";
233 };
234 };
235
236 flx5: flexcom@f0004000 {
237 compatible = "atmel,sama5d2-flexcom";
238 reg = <0xf0004000 0x200>;
239 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
240 #address-cells = <1>;
241 #size-cells = <1>;
242 ranges = <0x0 0xf0004000 0x800>;
243 status = "disabled";
244
245 uart5: serial@200 {
246 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
247 reg = <0x200 0x200>;
248 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
249 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
250 dmas = <&dma0
251 (AT91_XDMAC_DT_MEM_IF(0) |
252 AT91_XDMAC_DT_PER_IF(1) |
253 AT91_XDMAC_DT_PERID(10))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]254 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]255 (AT91_XDMAC_DT_MEM_IF(0) |
256 AT91_XDMAC_DT_PER_IF(1) |
257 AT91_XDMAC_DT_PERID(11))>;
258 dma-names = "tx", "rx";
259 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
260 clock-names = "usart";
261 atmel,use-dma-rx;
262 atmel,use-dma-tx;
263 atmel,fifo-size = <16>;
264 status = "disabled";
265 };
266
267 spi5: spi@400 {
268 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
269 reg = <0x400 0x200>;
270 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
271 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
272 clock-names = "spi_clk";
273 dmas = <&dma0
274 (AT91_XDMAC_DT_MEM_IF(0) |
275 AT91_XDMAC_DT_PER_IF(1) |
276 AT91_XDMAC_DT_PERID(10))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]277 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]278 (AT91_XDMAC_DT_MEM_IF(0) |
279 AT91_XDMAC_DT_PER_IF(1) |
280 AT91_XDMAC_DT_PERID(11))>;
281 dma-names = "tx", "rx";
282 atmel,fifo-size = <16>;
283 status = "disabled";
284 };
285
286 i2c5: i2c@600 {
287 compatible = "microchip,sam9x60-i2c";
288 reg = <0x600 0x200>;
289 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]290 #address-cells = <1>;
291 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]292 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
293 dmas = <&dma0
294 (AT91_XDMAC_DT_MEM_IF(0) |
295 AT91_XDMAC_DT_PER_IF(1) |
296 AT91_XDMAC_DT_PERID(10))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]297 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]298 (AT91_XDMAC_DT_MEM_IF(0) |
299 AT91_XDMAC_DT_PER_IF(1) |
300 AT91_XDMAC_DT_PERID(11))>;
301 dma-names = "tx", "rx";
302 atmel,fifo-size = <16>;
303 status = "disabled";
304 };
305 };
306
307 dma0: dma-controller@f0008000 {
308 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
309 reg = <0xf0008000 0x1000>;
310 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
311 #dma-cells = <1>;
312 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
313 clock-names = "dma_clk";
314 };
315
316 ssc: ssc@f0010000 {
317 compatible = "atmel,at91sam9g45-ssc";
318 reg = <0xf0010000 0x4000>;
319 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
320 dmas = <&dma0
321 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
322 AT91_XDMAC_DT_PERID(38))>,
323 <&dma0
324 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
325 AT91_XDMAC_DT_PERID(39))>;
326 dma-names = "tx", "rx";
327 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
328 clock-names = "pclk";
329 status = "disabled";
330 };
331
332 qspi: spi@f0014000 {
333 compatible = "microchip,sam9x60-qspi";
334 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
335 reg-names = "qspi_base", "qspi_mmap";
336 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
337 dmas = <&dma0
338 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
339 AT91_XDMAC_DT_PERID(26))>,
340 <&dma0
341 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
342 AT91_XDMAC_DT_PERID(27))>;
343 dma-names = "tx", "rx";
344 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
345 clock-names = "pclk", "qspick";
346 atmel,pmc = <&pmc>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 status = "disabled";
350 };
351
352 i2s: i2s@f001c000 {
353 compatible = "microchip,sam9x60-i2smcc";
354 reg = <0xf001c000 0x100>;
355 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
356 dmas = <&dma0
357 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
358 AT91_XDMAC_DT_PERID(36))>,
359 <&dma0
360 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
361 AT91_XDMAC_DT_PERID(37))>;
362 dma-names = "tx", "rx";
363 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
364 clock-names = "pclk", "gclk";
365 status = "disabled";
366 };
367
368 flx11: flexcom@f0020000 {
369 compatible = "atmel,sama5d2-flexcom";
370 reg = <0xf0020000 0x200>;
371 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
372 #address-cells = <1>;
373 #size-cells = <1>;
374 ranges = <0x0 0xf0020000 0x800>;
375 status = "disabled";
376
377 uart11: serial@200 {
378 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
379 reg = <0x200 0x200>;
380 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
381 dmas = <&dma0
382 (AT91_XDMAC_DT_MEM_IF(0) |
383 AT91_XDMAC_DT_PER_IF(1) |
384 AT91_XDMAC_DT_PERID(22))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]385 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]386 (AT91_XDMAC_DT_MEM_IF(0) |
387 AT91_XDMAC_DT_PER_IF(1) |
388 AT91_XDMAC_DT_PERID(23))>;
389 dma-names = "tx", "rx";
390 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
391 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]392 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]393 atmel,use-dma-rx;
394 atmel,use-dma-tx;
395 atmel,fifo-size = <16>;
396 status = "disabled";
397 };
398
399 i2c11: i2c@600 {
400 compatible = "microchip,sam9x60-i2c";
401 reg = <0x600 0x200>;
402 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]403 #address-cells = <1>;
404 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]405 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
406 dmas = <&dma0
407 (AT91_XDMAC_DT_MEM_IF(0) |
408 AT91_XDMAC_DT_PER_IF(1) |
409 AT91_XDMAC_DT_PERID(22))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]410 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]411 (AT91_XDMAC_DT_MEM_IF(0) |
412 AT91_XDMAC_DT_PER_IF(1) |
413 AT91_XDMAC_DT_PERID(23))>;
414 dma-names = "tx", "rx";
415 atmel,fifo-size = <16>;
416 status = "disabled";
417 };
418 };
419
420 flx12: flexcom@f0024000 {
421 compatible = "atmel,sama5d2-flexcom";
422 reg = <0xf0024000 0x200>;
423 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
424 #address-cells = <1>;
425 #size-cells = <1>;
426 ranges = <0x0 0xf0024000 0x800>;
427 status = "disabled";
428
429 uart12: serial@200 {
430 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
431 reg = <0x200 0x200>;
432 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
433 dmas = <&dma0
434 (AT91_XDMAC_DT_MEM_IF(0) |
435 AT91_XDMAC_DT_PER_IF(1) |
436 AT91_XDMAC_DT_PERID(24))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]437 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]438 (AT91_XDMAC_DT_MEM_IF(0) |
439 AT91_XDMAC_DT_PER_IF(1) |
440 AT91_XDMAC_DT_PERID(25))>;
441 dma-names = "tx", "rx";
442 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
443 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]444 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]445 atmel,use-dma-rx;
446 atmel,use-dma-tx;
447 atmel,fifo-size = <16>;
448 status = "disabled";
449 };
450
451 i2c12: i2c@600 {
452 compatible = "microchip,sam9x60-i2c";
453 reg = <0x600 0x200>;
454 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]455 #address-cells = <1>;
456 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]457 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
458 dmas = <&dma0
459 (AT91_XDMAC_DT_MEM_IF(0) |
460 AT91_XDMAC_DT_PER_IF(1) |
461 AT91_XDMAC_DT_PERID(24))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]462 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]463 (AT91_XDMAC_DT_MEM_IF(0) |
464 AT91_XDMAC_DT_PER_IF(1) |
465 AT91_XDMAC_DT_PERID(25))>;
466 dma-names = "tx", "rx";
467 atmel,fifo-size = <16>;
468 status = "disabled";
469 };
470 };
471
472 pit64b: timer@f0028000 {
473 compatible = "microchip,sam9x60-pit64b";
474 reg = <0xf0028000 0x100>;
475 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
476 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
477 clock-names = "pclk", "gclk";
478 };
479
480 sha: crypto@f002c000 {
481 compatible = "atmel,at91sam9g46-sha";
482 reg = <0xf002c000 0x100>;
483 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
484 dmas = <&dma0
485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
486 AT91_XDMAC_DT_PERID(34))>;
487 dma-names = "tx";
488 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
489 clock-names = "sha_clk";
490 };
491
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]492 trng: rng@f0030000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]493 compatible = "microchip,sam9x60-trng";
494 reg = <0xf0030000 0x100>;
495 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
496 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
497 };
498
499 aes: crypto@f0034000 {
500 compatible = "atmel,at91sam9g46-aes";
501 reg = <0xf0034000 0x100>;
502 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
503 dmas = <&dma0
504 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
505 AT91_XDMAC_DT_PERID(32))>,
506 <&dma0
507 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
508 AT91_XDMAC_DT_PERID(33))>;
509 dma-names = "tx", "rx";
510 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
511 clock-names = "aes_clk";
512 };
513
514 tdes: crypto@f0038000 {
515 compatible = "atmel,at91sam9g46-tdes";
516 reg = <0xf0038000 0x100>;
517 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
518 dmas = <&dma0
519 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
520 AT91_XDMAC_DT_PERID(31))>,
521 <&dma0
522 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
523 AT91_XDMAC_DT_PERID(30))>;
524 dma-names = "tx", "rx";
525 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
526 clock-names = "tdes_clk";
527 };
528
529 classd: classd@f003c000 {
530 compatible = "atmel,sama5d2-classd";
531 reg = <0xf003c000 0x100>;
532 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
533 dmas = <&dma0
534 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
535 AT91_XDMAC_DT_PERID(35))>;
536 dma-names = "tx";
537 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
538 clock-names = "pclk", "gclk";
539 status = "disabled";
540 };
541
542 can0: can@f8000000 {
543 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
544 reg = <0xf8000000 0x300>;
545 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
546 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
547 clock-names = "can_clk";
548 status = "disabled";
549 };
550
551 can1: can@f8004000 {
552 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
553 reg = <0xf8004000 0x300>;
554 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
555 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
556 clock-names = "can_clk";
557 status = "disabled";
558 };
559
560 tcb0: timer@f8008000 {
561 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
562 #address-cells = <1>;
563 #size-cells = <0>;
564 reg = <0xf8008000 0x100>;
565 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
566 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
567 clock-names = "t0_clk", "slow_clk";
568 };
569
570 tcb1: timer@f800c000 {
571 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
572 #address-cells = <1>;
573 #size-cells = <0>;
574 reg = <0xf800c000 0x100>;
575 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
576 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
577 clock-names = "t0_clk", "slow_clk";
578 };
579
580 flx6: flexcom@f8010000 {
581 compatible = "atmel,sama5d2-flexcom";
582 reg = <0xf8010000 0x200>;
583 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
584 #address-cells = <1>;
585 #size-cells = <1>;
586 ranges = <0x0 0xf8010000 0x800>;
587 status = "disabled";
588
589 uart6: serial@200 {
590 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
591 reg = <0x200 0x200>;
592 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
593 dmas = <&dma0
594 (AT91_XDMAC_DT_MEM_IF(0) |
595 AT91_XDMAC_DT_PER_IF(1) |
596 AT91_XDMAC_DT_PERID(12))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]597 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]598 (AT91_XDMAC_DT_MEM_IF(0) |
599 AT91_XDMAC_DT_PER_IF(1) |
600 AT91_XDMAC_DT_PERID(13))>;
601 dma-names = "tx", "rx";
602 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
603 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]604 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]605 atmel,use-dma-rx;
606 atmel,use-dma-tx;
607 atmel,fifo-size = <16>;
608 status = "disabled";
609 };
610
611 i2c6: i2c@600 {
612 compatible = "microchip,sam9x60-i2c";
613 reg = <0x600 0x200>;
614 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]615 #address-cells = <1>;
616 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]617 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
618 dmas = <&dma0
619 (AT91_XDMAC_DT_MEM_IF(0) |
620 AT91_XDMAC_DT_PER_IF(1) |
621 AT91_XDMAC_DT_PERID(12))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]622 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]623 (AT91_XDMAC_DT_MEM_IF(0) |
624 AT91_XDMAC_DT_PER_IF(1) |
625 AT91_XDMAC_DT_PERID(13))>;
626 dma-names = "tx", "rx";
627 atmel,fifo-size = <16>;
628 status = "disabled";
629 };
630 };
631
632 flx7: flexcom@f8014000 {
633 compatible = "atmel,sama5d2-flexcom";
634 reg = <0xf8014000 0x200>;
635 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
636 #address-cells = <1>;
637 #size-cells = <1>;
638 ranges = <0x0 0xf8014000 0x800>;
639 status = "disabled";
640
641 uart7: serial@200 {
642 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
643 reg = <0x200 0x200>;
644 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
645 dmas = <&dma0
646 (AT91_XDMAC_DT_MEM_IF(0) |
647 AT91_XDMAC_DT_PER_IF(1) |
648 AT91_XDMAC_DT_PERID(14))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]649 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]650 (AT91_XDMAC_DT_MEM_IF(0) |
651 AT91_XDMAC_DT_PER_IF(1) |
652 AT91_XDMAC_DT_PERID(15))>;
653 dma-names = "tx", "rx";
654 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
655 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]656 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]657 atmel,use-dma-rx;
658 atmel,use-dma-tx;
659 atmel,fifo-size = <16>;
660 status = "disabled";
661 };
662
663 i2c7: i2c@600 {
664 compatible = "microchip,sam9x60-i2c";
665 reg = <0x600 0x200>;
666 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]667 #address-cells = <1>;
668 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]669 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
670 dmas = <&dma0
671 (AT91_XDMAC_DT_MEM_IF(0) |
672 AT91_XDMAC_DT_PER_IF(1) |
673 AT91_XDMAC_DT_PERID(14))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]674 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]675 (AT91_XDMAC_DT_MEM_IF(0) |
676 AT91_XDMAC_DT_PER_IF(1) |
677 AT91_XDMAC_DT_PERID(15))>;
678 dma-names = "tx", "rx";
679 atmel,fifo-size = <16>;
680 status = "disabled";
681 };
682 };
683
684 flx8: flexcom@f8018000 {
685 compatible = "atmel,sama5d2-flexcom";
686 reg = <0xf8018000 0x200>;
687 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
688 #address-cells = <1>;
689 #size-cells = <1>;
690 ranges = <0x0 0xf8018000 0x800>;
691 status = "disabled";
692
693 uart8: serial@200 {
694 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
695 reg = <0x200 0x200>;
696 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
697 dmas = <&dma0
698 (AT91_XDMAC_DT_MEM_IF(0) |
699 AT91_XDMAC_DT_PER_IF(1) |
700 AT91_XDMAC_DT_PERID(16))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]701 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]702 (AT91_XDMAC_DT_MEM_IF(0) |
703 AT91_XDMAC_DT_PER_IF(1) |
704 AT91_XDMAC_DT_PERID(17))>;
705 dma-names = "tx", "rx";
706 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
707 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]708 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]709 atmel,use-dma-rx;
710 atmel,use-dma-tx;
711 atmel,fifo-size = <16>;
712 status = "disabled";
713 };
714
715 i2c8: i2c@600 {
716 compatible = "microchip,sam9x60-i2c";
717 reg = <0x600 0x200>;
718 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]719 #address-cells = <1>;
720 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]721 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
722 dmas = <&dma0
723 (AT91_XDMAC_DT_MEM_IF(0) |
724 AT91_XDMAC_DT_PER_IF(1) |
725 AT91_XDMAC_DT_PERID(16))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]726 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]727 (AT91_XDMAC_DT_MEM_IF(0) |
728 AT91_XDMAC_DT_PER_IF(1) |
729 AT91_XDMAC_DT_PERID(17))>;
730 dma-names = "tx", "rx";
731 atmel,fifo-size = <16>;
732 status = "disabled";
733 };
734 };
735
736 flx0: flexcom@f801c000 {
737 compatible = "atmel,sama5d2-flexcom";
738 reg = <0xf801c000 0x200>;
739 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
740 #address-cells = <1>;
741 #size-cells = <1>;
742 ranges = <0x0 0xf801c000 0x800>;
743 status = "disabled";
744
745 uart0: serial@200 {
746 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
747 reg = <0x200 0x200>;
748 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
749 dmas = <&dma0
750 (AT91_XDMAC_DT_MEM_IF(0) |
751 AT91_XDMAC_DT_PER_IF(1) |
752 AT91_XDMAC_DT_PERID(0))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]753 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]754 (AT91_XDMAC_DT_MEM_IF(0) |
755 AT91_XDMAC_DT_PER_IF(1) |
756 AT91_XDMAC_DT_PERID(1))>;
757 dma-names = "tx", "rx";
758 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
759 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]760 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]761 atmel,use-dma-rx;
762 atmel,use-dma-tx;
763 atmel,fifo-size = <16>;
764 status = "disabled";
765 };
766
767 spi0: spi@400 {
768 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
769 reg = <0x400 0x200>;
770 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
771 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
772 clock-names = "spi_clk";
773 dmas = <&dma0
774 (AT91_XDMAC_DT_MEM_IF(0) |
775 AT91_XDMAC_DT_PER_IF(1) |
776 AT91_XDMAC_DT_PERID(0))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]777 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]778 (AT91_XDMAC_DT_MEM_IF(0) |
779 AT91_XDMAC_DT_PER_IF(1) |
780 AT91_XDMAC_DT_PERID(1))>;
781 dma-names = "tx", "rx";
782 atmel,fifo-size = <16>;
783 status = "disabled";
784 };
785
786 i2c0: i2c@600 {
787 compatible = "microchip,sam9x60-i2c";
788 reg = <0x600 0x200>;
789 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]790 #address-cells = <1>;
791 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]792 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
793 dmas = <&dma0
794 (AT91_XDMAC_DT_MEM_IF(0) |
795 AT91_XDMAC_DT_PER_IF(1) |
796 AT91_XDMAC_DT_PERID(0))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]797 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]798 (AT91_XDMAC_DT_MEM_IF(0) |
799 AT91_XDMAC_DT_PER_IF(1) |
800 AT91_XDMAC_DT_PERID(1))>;
801 dma-names = "tx", "rx";
802 atmel,fifo-size = <16>;
803 status = "disabled";
804 };
805 };
806
807 flx1: flexcom@f8020000 {
808 compatible = "atmel,sama5d2-flexcom";
809 reg = <0xf8020000 0x200>;
810 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
811 #address-cells = <1>;
812 #size-cells = <1>;
813 ranges = <0x0 0xf8020000 0x800>;
814 status = "disabled";
815
816 uart1: serial@200 {
817 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
818 reg = <0x200 0x200>;
819 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
820 dmas = <&dma0
821 (AT91_XDMAC_DT_MEM_IF(0) |
822 AT91_XDMAC_DT_PER_IF(1) |
823 AT91_XDMAC_DT_PERID(2))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]824 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]825 (AT91_XDMAC_DT_MEM_IF(0) |
826 AT91_XDMAC_DT_PER_IF(1) |
827 AT91_XDMAC_DT_PERID(3))>;
828 dma-names = "tx", "rx";
829 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
830 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]831 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]832 atmel,use-dma-rx;
833 atmel,use-dma-tx;
834 atmel,fifo-size = <16>;
835 status = "disabled";
836 };
837
838 spi1: spi@400 {
839 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
840 reg = <0x400 0x200>;
841 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
842 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
843 clock-names = "spi_clk";
844 dmas = <&dma0
845 (AT91_XDMAC_DT_MEM_IF(0) |
846 AT91_XDMAC_DT_PER_IF(1) |
847 AT91_XDMAC_DT_PERID(2))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]848 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]849 (AT91_XDMAC_DT_MEM_IF(0) |
850 AT91_XDMAC_DT_PER_IF(1) |
851 AT91_XDMAC_DT_PERID(3))>;
852 dma-names = "tx", "rx";
853 atmel,fifo-size = <16>;
854 status = "disabled";
855 };
856
857 i2c1: i2c@600 {
858 compatible = "microchip,sam9x60-i2c";
859 reg = <0x600 0x200>;
860 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]861 #address-cells = <1>;
862 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]863 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
864 dmas = <&dma0
865 (AT91_XDMAC_DT_MEM_IF(0) |
866 AT91_XDMAC_DT_PER_IF(1) |
867 AT91_XDMAC_DT_PERID(2))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]868 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]869 (AT91_XDMAC_DT_MEM_IF(0) |
870 AT91_XDMAC_DT_PER_IF(1) |
871 AT91_XDMAC_DT_PERID(3))>;
872 dma-names = "tx", "rx";
873 atmel,fifo-size = <16>;
874 status = "disabled";
875 };
876 };
877
878 flx2: flexcom@f8024000 {
879 compatible = "atmel,sama5d2-flexcom";
880 reg = <0xf8024000 0x200>;
881 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
882 #address-cells = <1>;
883 #size-cells = <1>;
884 ranges = <0x0 0xf8024000 0x800>;
885 status = "disabled";
886
887 uart2: serial@200 {
888 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
889 reg = <0x200 0x200>;
890 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
891 dmas = <&dma0
892 (AT91_XDMAC_DT_MEM_IF(0) |
893 AT91_XDMAC_DT_PER_IF(1) |
894 AT91_XDMAC_DT_PERID(4))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]895 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]896 (AT91_XDMAC_DT_MEM_IF(0) |
897 AT91_XDMAC_DT_PER_IF(1) |
898 AT91_XDMAC_DT_PERID(5))>;
899 dma-names = "tx", "rx";
900 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
901 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]902 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]903 atmel,use-dma-rx;
904 atmel,use-dma-tx;
905 atmel,fifo-size = <16>;
906 status = "disabled";
907 };
908
909 spi2: spi@400 {
910 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
911 reg = <0x400 0x200>;
912 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
913 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
914 clock-names = "spi_clk";
915 dmas = <&dma0
916 (AT91_XDMAC_DT_MEM_IF(0) |
917 AT91_XDMAC_DT_PER_IF(1) |
918 AT91_XDMAC_DT_PERID(4))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]919 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]920 (AT91_XDMAC_DT_MEM_IF(0) |
921 AT91_XDMAC_DT_PER_IF(1) |
922 AT91_XDMAC_DT_PERID(5))>;
923 dma-names = "tx", "rx";
924 atmel,fifo-size = <16>;
925 status = "disabled";
926 };
927
928 i2c2: i2c@600 {
929 compatible = "microchip,sam9x60-i2c";
930 reg = <0x600 0x200>;
931 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]932 #address-cells = <1>;
933 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]934 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
935 dmas = <&dma0
936 (AT91_XDMAC_DT_MEM_IF(0) |
937 AT91_XDMAC_DT_PER_IF(1) |
938 AT91_XDMAC_DT_PERID(4))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]939 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]940 (AT91_XDMAC_DT_MEM_IF(0) |
941 AT91_XDMAC_DT_PER_IF(1) |
942 AT91_XDMAC_DT_PERID(5))>;
943 dma-names = "tx", "rx";
944 atmel,fifo-size = <16>;
945 status = "disabled";
946 };
947 };
948
949 flx3: flexcom@f8028000 {
950 compatible = "atmel,sama5d2-flexcom";
951 reg = <0xf8028000 0x200>;
952 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
953 #address-cells = <1>;
954 #size-cells = <1>;
955 ranges = <0x0 0xf8028000 0x800>;
956 status = "disabled";
957
958 uart3: serial@200 {
959 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
960 reg = <0x200 0x200>;
961 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
962 dmas = <&dma0
963 (AT91_XDMAC_DT_MEM_IF(0) |
964 AT91_XDMAC_DT_PER_IF(1) |
965 AT91_XDMAC_DT_PERID(6))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]966 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]967 (AT91_XDMAC_DT_MEM_IF(0) |
968 AT91_XDMAC_DT_PER_IF(1) |
969 AT91_XDMAC_DT_PERID(7))>;
970 dma-names = "tx", "rx";
971 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
972 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]973 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]974 atmel,use-dma-rx;
975 atmel,use-dma-tx;
976 atmel,fifo-size = <16>;
977 status = "disabled";
978 };
979
980 spi3: spi@400 {
981 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
982 reg = <0x400 0x200>;
983 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
984 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
985 clock-names = "spi_clk";
986 dmas = <&dma0
987 (AT91_XDMAC_DT_MEM_IF(0) |
988 AT91_XDMAC_DT_PER_IF(1) |
989 AT91_XDMAC_DT_PERID(6))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]990 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]991 (AT91_XDMAC_DT_MEM_IF(0) |
992 AT91_XDMAC_DT_PER_IF(1) |
993 AT91_XDMAC_DT_PERID(7))>;
994 dma-names = "tx", "rx";
995 atmel,fifo-size = <16>;
996 status = "disabled";
997 };
998
999 i2c3: i2c@600 {
1000 compatible = "microchip,sam9x60-i2c";
1001 reg = <0x600 0x200>;
1002 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1003 #address-cells = <1>;
1004 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1005 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
1006 dmas = <&dma0
1007 (AT91_XDMAC_DT_MEM_IF(0) |
1008 AT91_XDMAC_DT_PER_IF(1) |
1009 AT91_XDMAC_DT_PERID(6))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1010 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1011 (AT91_XDMAC_DT_MEM_IF(0) |
1012 AT91_XDMAC_DT_PER_IF(1) |
1013 AT91_XDMAC_DT_PERID(7))>;
1014 dma-names = "tx", "rx";
1015 atmel,fifo-size = <16>;
1016 status = "disabled";
1017 };
1018 };
1019
1020 macb0: ethernet@f802c000 {
1021 compatible = "cdns,sam9x60-macb", "cdns,macb";
1022 reg = <0xf802c000 0x1000>;
1023 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
1024 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
1025 clock-names = "hclk", "pclk";
1026 status = "disabled";
1027 };
1028
1029 macb1: ethernet@f8030000 {
1030 compatible = "cdns,sam9x60-macb", "cdns,macb";
1031 reg = <0xf8030000 0x1000>;
1032 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
1033 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
1034 clock-names = "hclk", "pclk";
1035 status = "disabled";
1036 };
1037
1038 pwm0: pwm@f8034000 {
1039 compatible = "microchip,sam9x60-pwm";
1040 reg = <0xf8034000 0x300>;
1041 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1042 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1043 #pwm-cells = <3>;
1044 status = "disabled";
1045 };
1046
1047 hlcdc: hlcdc@f8038000 {
1048 compatible = "microchip,sam9x60-hlcdc";
1049 reg = <0xf8038000 0x4000>;
1050 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
1051 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
1052 clock-names = "periph_clk","sys_clk", "slow_clk";
1053 assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
1054 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
1055 status = "disabled";
1056
1057 hlcdc-display-controller {
1058 compatible = "atmel,hlcdc-display-controller";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061
1062 port@0 {
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 reg = <0>;
1066 };
1067 };
1068
1069 hlcdc_pwm: hlcdc-pwm {
1070 compatible = "atmel,hlcdc-pwm";
1071 #pwm-cells = <3>;
1072 };
1073 };
1074
1075 flx9: flexcom@f8040000 {
1076 compatible = "atmel,sama5d2-flexcom";
1077 reg = <0xf8040000 0x200>;
1078 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1079 #address-cells = <1>;
1080 #size-cells = <1>;
1081 ranges = <0x0 0xf8040000 0x800>;
1082 status = "disabled";
1083
1084 uart9: serial@200 {
1085 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
1086 reg = <0x200 0x200>;
1087 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
1088 dmas = <&dma0
1089 (AT91_XDMAC_DT_MEM_IF(0) |
1090 AT91_XDMAC_DT_PER_IF(1) |
1091 AT91_XDMAC_DT_PERID(18))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1092 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1093 (AT91_XDMAC_DT_MEM_IF(0) |
1094 AT91_XDMAC_DT_PER_IF(1) |
1095 AT91_XDMAC_DT_PERID(19))>;
1096 dma-names = "tx", "rx";
1097 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1098 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]1099 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1100 atmel,use-dma-rx;
1101 atmel,use-dma-tx;
1102 atmel,fifo-size = <16>;
1103 status = "disabled";
1104 };
1105
1106 i2c9: i2c@600 {
1107 compatible = "microchip,sam9x60-i2c";
1108 reg = <0x600 0x200>;
1109 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1110 #address-cells = <1>;
1111 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1112 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1113 dmas = <&dma0
1114 (AT91_XDMAC_DT_MEM_IF(0) |
1115 AT91_XDMAC_DT_PER_IF(1) |
1116 AT91_XDMAC_DT_PERID(18))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1117 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1118 (AT91_XDMAC_DT_MEM_IF(0) |
1119 AT91_XDMAC_DT_PER_IF(1) |
1120 AT91_XDMAC_DT_PERID(19))>;
1121 dma-names = "tx", "rx";
1122 atmel,fifo-size = <16>;
1123 status = "disabled";
1124 };
1125 };
1126
1127 flx10: flexcom@f8044000 {
1128 compatible = "atmel,sama5d2-flexcom";
1129 reg = <0xf8044000 0x200>;
1130 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1131 #address-cells = <1>;
1132 #size-cells = <1>;
1133 ranges = <0x0 0xf8044000 0x800>;
1134 status = "disabled";
1135
1136 uart10: serial@200 {
1137 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
1138 reg = <0x200 0x200>;
1139 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
1140 dmas = <&dma0
1141 (AT91_XDMAC_DT_MEM_IF(0) |
1142 AT91_XDMAC_DT_PER_IF(1) |
1143 AT91_XDMAC_DT_PERID(20))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1144 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1145 (AT91_XDMAC_DT_MEM_IF(0) |
1146 AT91_XDMAC_DT_PER_IF(1) |
1147 AT91_XDMAC_DT_PERID(21))>;
1148 dma-names = "tx", "rx";
1149 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1150 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]1151 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1152 atmel,use-dma-rx;
1153 atmel,use-dma-tx;
1154 atmel,fifo-size = <16>;
1155 status = "disabled";
1156 };
1157
1158 i2c10: i2c@600 {
1159 compatible = "microchip,sam9x60-i2c";
1160 reg = <0x600 0x200>;
1161 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1162 #address-cells = <1>;
1163 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1164 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1165 dmas = <&dma0
1166 (AT91_XDMAC_DT_MEM_IF(0) |
1167 AT91_XDMAC_DT_PER_IF(1) |
1168 AT91_XDMAC_DT_PERID(20))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1169 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1170 (AT91_XDMAC_DT_MEM_IF(0) |
1171 AT91_XDMAC_DT_PER_IF(1) |
1172 AT91_XDMAC_DT_PERID(21))>;
1173 dma-names = "tx", "rx";
1174 atmel,fifo-size = <16>;
1175 status = "disabled";
1176 };
1177 };
1178
1179 isi: isi@f8048000 {
1180 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
1181 reg = <0xf8048000 0x100>;
1182 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
1183 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
1184 clock-names = "isi_clk";
1185 status = "disabled";
1186 port {
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 };
1190 };
1191
1192 adc: adc@f804c000 {
1193 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
1194 reg = <0xf804c000 0x100>;
1195 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
1196 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
1197 clock-names = "adc_clk";
1198 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
1199 dma-names = "rx";
1200 atmel,min-sample-rate-hz = <200000>;
1201 atmel,max-sample-rate-hz = <20000000>;
1202 atmel,startup-time-ms = <4>;
1203 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1204 #io-channel-cells = <1>;
1205 status = "disabled";
1206 };
1207
1208 sfr: sfr@f8050000 {
1209 compatible = "microchip,sam9x60-sfr", "syscon";
1210 reg = <0xf8050000 0x100>;
1211 };
1212
1213 matrix: matrix@ffffde00 {
1214 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
1215 reg = <0xffffde00 0x200>;
1216 };
1217
1218 pmecc: ecc-engine@ffffe000 {
1219 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
1220 reg = <0xffffe000 0x300>,
1221 <0xffffe600 0x100>;
1222 };
1223
1224 mpddrc: mpddrc@ffffe800 {
1225 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
1226 reg = <0xffffe800 0x200>;
1227 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
1228 clock-names = "ddrck", "mpddr";
1229 };
1230
1231 smc: smc@ffffea00 {
1232 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
1233 reg = <0xffffea00 0x100>;
1234 };
1235
1236 aic: interrupt-controller@fffff100 {
1237 compatible = "microchip,sam9x60-aic";
1238 #interrupt-cells = <3>;
1239 interrupt-controller;
1240 reg = <0xfffff100 0x100>;
1241 atmel,external-irqs = <31>;
1242 };
1243
1244 dbgu: serial@fffff200 {
1245 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1246 reg = <0xfffff200 0x200>;
1247 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
1248 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
1249 dmas = <&dma0
1250 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1251 AT91_XDMAC_DT_PERID(28))>,
1252 <&dma0
1253 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1254 AT91_XDMAC_DT_PERID(29))>;
1255 dma-names = "tx", "rx";
1256 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
1257 clock-names = "usart";
1258 status = "disabled";
1259 };
1260
1261 pinctrl: pinctrl@fffff400 {
1262 #address-cells = <1>;
1263 #size-cells = <1>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1264 compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1265 ranges = <0xfffff400 0xfffff400 0x800>;
1266
1267 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
1268 atmel,mux-mask = <
1269 /* A B C */
1270 0xffffffff 0xffe03fff 0xef00019d /* pioA */
1271 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
1272 0xffffffff 0xffffffff 0xf83fffff /* pioC */
1273 0x003fffff 0x003f8000 0x00000000 /* pioD */
1274 >;
1275
1276 pioA: gpio@fffff400 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1277 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1278 reg = <0xfffff400 0x200>;
1279 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
1280 #gpio-cells = <2>;
1281 gpio-controller;
1282 interrupt-controller;
1283 #interrupt-cells = <2>;
1284 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
1285 };
1286
1287 pioB: gpio@fffff600 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1288 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1289 reg = <0xfffff600 0x200>;
1290 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
1291 #gpio-cells = <2>;
1292 gpio-controller;
1293 #gpio-lines = <26>;
1294 interrupt-controller;
1295 #interrupt-cells = <2>;
1296 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
1297 };
1298
1299 pioC: gpio@fffff800 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1300 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1301 reg = <0xfffff800 0x200>;
1302 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
1303 #gpio-cells = <2>;
1304 gpio-controller;
1305 interrupt-controller;
1306 #interrupt-cells = <2>;
1307 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
1308 };
1309
1310 pioD: gpio@fffffa00 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1311 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1312 reg = <0xfffffa00 0x200>;
1313 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
1314 #gpio-cells = <2>;
1315 gpio-controller;
1316 #gpio-lines = <22>;
1317 interrupt-controller;
1318 #interrupt-cells = <2>;
1319 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
1320 };
1321 };
1322
1323 pmc: clock-controller@fffffc00 {
1324 compatible = "microchip,sam9x60-pmc", "syscon";
1325 reg = <0xfffffc00 0x200>;
1326 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1327 #clock-cells = <2>;
1328 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1329 clock-names = "td_slck", "md_slck", "main_xtal";
1330 };
1331
1332 reset_controller: reset-controller@fffffe00 {
1333 compatible = "microchip,sam9x60-rstc";
1334 reg = <0xfffffe00 0x10>;
1335 clocks = <&clk32k 0>;
1336 };
1337
1338 shutdown_controller: poweroff@fffffe10 {
1339 compatible = "microchip,sam9x60-shdwc";
1340 reg = <0xfffffe10 0x10>;
1341 clocks = <&clk32k 0>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1344 atmel,wakeup-rtc-timer;
1345 atmel,wakeup-rtt-timer;
1346 status = "disabled";
1347 };
1348
1349 rtt: rtc@fffffe20 {
1350 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
1351 reg = <0xfffffe20 0x20>;
1352 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1353 clocks = <&clk32k 1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1354 };
1355
1356 pit: timer@fffffe40 {
1357 compatible = "atmel,at91sam9260-pit";
1358 reg = <0xfffffe40 0x10>;
1359 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1360 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
1361 };
1362
1363 clk32k: clock-controller@fffffe50 {
1364 compatible = "microchip,sam9x60-sckc";
1365 reg = <0xfffffe50 0x4>;
1366 clocks = <&slow_xtal>;
1367 #clock-cells = <1>;
1368 };
1369
1370 gpbr: syscon@fffffe60 {
1371 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
1372 reg = <0xfffffe60 0x10>;
1373 };
1374
1375 rtc: rtc@fffffea8 {
1376 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
1377 reg = <0xfffffea8 0x100>;
1378 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1379 clocks = <&clk32k 1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1380 };
1381
1382 watchdog: watchdog@ffffff80 {
1383 compatible = "microchip,sam9x60-wdt";
1384 reg = <0xffffff80 0x24>;
1385 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1386 clocks = <&clk32k 0>;
1387 status = "disabled";
1388 };
1389 };
1390 };
1391};