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git01.mediatek.com / filogic / uboot / 844493d7e99cb795f3e28130ee09ba7a6441162f / . / src / arm / aspeed / aspeed-bmc-ampere-mtmitchell.dts
blob: 0295f5adcfbc8414b061bffc484bd1cdc65330f3 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2022, Ampere Computing LLC
3
4/dts-v1/;
5
6#include "aspeed-g6.dtsi"
7#include <dt-bindings/i2c/i2c.h>
8#include <dt-bindings/gpio/aspeed-gpio.h>
9
10/ {
11 model = "Ampere Mt.Mitchell BMC";
12 compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
13
14 aliases {
15 serial7 = &uart8;
16 serial8 = &uart9;
17
18 /*
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]19 * I2C temperature alias port
20 */
21 i2c20 = &i2c4_bus70_chn0;
22 i2c21 = &i2c4_bus70_chn1;
23 i2c22 = &i2c4_bus70_chn2;
24 i2c23 = &i2c4_bus70_chn3;
25
26 /*
27 * i2c bus 30-31 assigned to OCP slot 0-1
28 */
29 i2c30 = &ocpslot_0;
30 i2c31 = &ocpslot_1;
31
32 /*
33 * i2c bus 32-33 assigned to Riser slot 0-1
34 */
35 i2c32 = &i2c_riser0;
36 i2c33 = &i2c_riser1;
37
38 /*
39 * i2c bus 38-39 assigned to FRU on Riser slot 0-1
40 */
41 i2c38 = &i2c_riser0_chn_0;
42 i2c39 = &i2c_riser1_chn_0;
43
44 /*
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]45 * I2C NVMe alias port
46 */
47 i2c100 = &backplane_0;
48 i2c48 = &nvmeslot_0;
49 i2c49 = &nvmeslot_1;
50 i2c50 = &nvmeslot_2;
51 i2c51 = &nvmeslot_3;
52 i2c52 = &nvmeslot_4;
53 i2c53 = &nvmeslot_5;
54 i2c54 = &nvmeslot_6;
55 i2c55 = &nvmeslot_7;
56
57 i2c101 = &backplane_1;
58 i2c56 = &nvmeslot_8;
59 i2c57 = &nvmeslot_9;
60 i2c58 = &nvmeslot_10;
61 i2c59 = &nvmeslot_11;
62 i2c60 = &nvmeslot_12;
63 i2c61 = &nvmeslot_13;
64 i2c62 = &nvmeslot_14;
65 i2c63 = &nvmeslot_15;
66
67 i2c102 = &backplane_2;
68 i2c64 = &nvmeslot_16;
69 i2c65 = &nvmeslot_17;
70 i2c66 = &nvmeslot_18;
71 i2c67 = &nvmeslot_19;
72 i2c68 = &nvmeslot_20;
73 i2c69 = &nvmeslot_21;
74 i2c70 = &nvmeslot_22;
75 i2c71 = &nvmeslot_23;
76
77 i2c80 = &nvme_m2_0;
78 i2c81 = &nvme_m2_1;
79 };
80
81 chosen {
82 stdout-path = &uart5;
83 };
84
85 memory@80000000 {
86 device_type = "memory";
87 reg = <0x80000000 0x80000000>;
88 };
89
90 reserved-memory {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges;
94
95 gfx_memory: framebuffer {
96 size = <0x01000000>;
97 alignment = <0x01000000>;
98 compatible = "shared-dma-pool";
99 reusable;
100 };
101
102 video_engine_memory: video {
103 size = <0x04000000>;
104 alignment = <0x01000000>;
105 compatible = "shared-dma-pool";
106 reusable;
107 };
108
109 vga_memory: region@bf000000 {
110 no-map;
111 compatible = "shared-dma-pool";
112 reg = <0xbf000000 0x01000000>; /* 16M */
113 };
114 };
115
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]116 leds {
117 compatible = "gpio-leds";
118 /*
119 * Use gpio-leds to configure GPIOW5 (bmc-ready) pin to be reseted when
120 * watchdog timeout.
121 */
122 led-bmc-ready {
123 gpios = <&gpio0 ASPEED_GPIO(W, 5) (GPIO_ACTIVE_HIGH | GPIO_TRANSITORY)>;
124 };
125
126 led-sw-heartbeat {
127 gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_HIGH>;
128 };
129
130 led-identify {
131 gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
132 };
133
134 led-fault {
135 gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
136 };
137
138 led-fan-fault {
139 gpios = <&gpio_expander1 0 GPIO_ACTIVE_HIGH>;
140 };
141
142 led-psu-fault {
143 gpios = <&gpio_expander1 1 GPIO_ACTIVE_HIGH>;
144 };
145 };
146
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]147 voltage_mon_reg: voltage-mon-regulator {
148 compatible = "regulator-fixed";
149 regulator-name = "ltc2497_reg";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 };
154
155 gpioI5mux: mux-controller {
156 compatible = "gpio-mux";
157 #mux-control-cells = <0>;
158 mux-gpios = <&gpio0 ASPEED_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
159 };
160
161 adc0mux: adc0mux {
162 compatible = "io-channel-mux";
163 io-channels = <&adc_i2c_0 0>;
164 #io-channel-cells = <1>;
165 io-channel-names = "parent";
166 mux-controls = <&gpioI5mux>;
167 settle-time-us = <10000>;
168 channels = "s0", "s1";
169 };
170
171 adc1mux: adc1mux {
172 compatible = "io-channel-mux";
173 io-channels = <&adc_i2c_0 1>;
174 #io-channel-cells = <1>;
175 io-channel-names = "parent";
176 mux-controls = <&gpioI5mux>;
177 settle-time-us = <10000>;
178 channels = "s0", "s1";
179 };
180
181 adc2mux: adc2mux {
182 compatible = "io-channel-mux";
183 io-channels = <&adc_i2c_0 2>;
184 #io-channel-cells = <1>;
185 io-channel-names = "parent";
186 mux-controls = <&gpioI5mux>;
187 settle-time-us = <10000>;
188 channels = "s0", "s1";
189 };
190
191 adc3mux: adc3mux {
192 compatible = "io-channel-mux";
193 io-channels = <&adc_i2c_0 3>;
194 #io-channel-cells = <1>;
195 io-channel-names = "parent";
196 mux-controls = <&gpioI5mux>;
197 settle-time-us = <10000>;
198 channels = "s0", "s1";
199 };
200
201 adc4mux: adc4mux {
202 compatible = "io-channel-mux";
203 io-channels = <&adc_i2c_0 4>;
204 #io-channel-cells = <1>;
205 io-channel-names = "parent";
206 mux-controls = <&gpioI5mux>;
207 settle-time-us = <10000>;
208 channels = "s0", "s1";
209 };
210
211 adc5mux: adc5mux {
212 compatible = "io-channel-mux";
213 io-channels = <&adc_i2c_0 5>;
214 #io-channel-cells = <1>;
215 io-channel-names = "parent";
216 mux-controls = <&gpioI5mux>;
217 settle-time-us = <10000>;
218 channels = "s0", "s1";
219 };
220
221 adc6mux: adc6mux {
222 compatible = "io-channel-mux";
223 io-channels = <&adc_i2c_0 6>;
224 #io-channel-cells = <1>;
225 io-channel-names = "parent";
226 mux-controls = <&gpioI5mux>;
227 settle-time-us = <10000>;
228 channels = "s0", "s1";
229 };
230
231 adc7mux: adc7mux {
232 compatible = "io-channel-mux";
233 io-channels = <&adc_i2c_0 7>;
234 #io-channel-cells = <1>;
235 io-channel-names = "parent";
236 mux-controls = <&gpioI5mux>;
237 settle-time-us = <10000>;
238 channels = "s0", "s1";
239 };
240
241 adc8mux: adc8mux {
242 compatible = "io-channel-mux";
243 io-channels = <&adc_i2c_0 8>;
244 #io-channel-cells = <1>;
245 io-channel-names = "parent";
246 mux-controls = <&gpioI5mux>;
247 settle-time-us = <10000>;
248 channels = "s0", "s1";
249 };
250
251 adc9mux: adc9mux {
252 compatible = "io-channel-mux";
253 io-channels = <&adc_i2c_0 9>;
254 #io-channel-cells = <1>;
255 io-channel-names = "parent";
256 mux-controls = <&gpioI5mux>;
257 settle-time-us = <10000>;
258 channels = "s0", "s1";
259 };
260
261 adc10mux: adc10mux {
262 compatible = "io-channel-mux";
263 io-channels = <&adc_i2c_0 10>;
264 #io-channel-cells = <1>;
265 io-channel-names = "parent";
266 mux-controls = <&gpioI5mux>;
267 settle-time-us = <10000>;
268 channels = "s0", "s1";
269 };
270
271 adc11mux: adc11mux {
272 compatible = "io-channel-mux";
273 io-channels = <&adc_i2c_0 11>;
274 #io-channel-cells = <1>;
275 io-channel-names = "parent";
276 mux-controls = <&gpioI5mux>;
277 settle-time-us = <10000>;
278 channels = "s0", "s1";
279 };
280
281 adc12mux: adc12mux {
282 compatible = "io-channel-mux";
283 io-channels = <&adc_i2c_0 12>;
284 #io-channel-cells = <1>;
285 io-channel-names = "parent";
286 mux-controls = <&gpioI5mux>;
287 settle-time-us = <10000>;
288 channels = "s0", "s1";
289 };
290
291 adc13mux: adc13mux {
292 compatible = "io-channel-mux";
293 io-channels = <&adc_i2c_0 13>;
294 #io-channel-cells = <1>;
295 io-channel-names = "parent";
296 mux-controls = <&gpioI5mux>;
297 settle-time-us = <10000>;
298 channels = "s0", "s1";
299 };
300
301 adc14mux: adc14mux {
302 compatible = "io-channel-mux";
303 io-channels = <&adc_i2c_0 14>;
304 #io-channel-cells = <1>;
305 io-channel-names = "parent";
306 mux-controls = <&gpioI5mux>;
307 settle-time-us = <10000>;
308 channels = "s0", "s1";
309 };
310
311 adc15mux: adc15mux {
312 compatible = "io-channel-mux";
313 io-channels = <&adc_i2c_0 15>;
314 #io-channel-cells = <1>;
315 io-channel-names = "parent";
316 mux-controls = <&gpioI5mux>;
317 settle-time-us = <10000>;
318 channels = "s0", "s1";
319 };
320
321 iio-hwmon {
322 compatible = "iio-hwmon";
323 io-channels = <&adc0mux 0>, <&adc0mux 1>,
324 <&adc1mux 0>, <&adc1mux 1>,
325 <&adc2mux 0>, <&adc2mux 1>,
326 <&adc3mux 0>, <&adc3mux 1>,
327 <&adc4mux 0>, <&adc4mux 1>,
328 <&adc5mux 0>, <&adc5mux 1>,
329 <&adc6mux 0>, <&adc6mux 1>,
330 <&adc7mux 0>, <&adc7mux 1>,
331 <&adc8mux 0>, <&adc8mux 1>,
332 <&adc9mux 0>, <&adc9mux 1>,
333 <&adc10mux 0>, <&adc10mux 1>,
334 <&adc11mux 0>, <&adc11mux 1>,
335 <&adc12mux 0>, <&adc12mux 1>,
336 <&adc13mux 0>, <&adc13mux 1>,
337 <&adc14mux 0>, <&adc14mux 1>,
338 <&adc15mux 0>, <&adc15mux 1>,
339 <&adc_i2c_1 0>, <&adc_i2c_1 1>,
340 <&adc_i2c_1 2>, <&adc_i2c_1 3>,
341 <&adc_i2c_1 4>, <&adc_i2c_1 5>,
342 <&adc_i2c_1 6>, <&adc_i2c_1 7>,
343 <&adc_i2c_1 8>, <&adc_i2c_1 9>,
344 <&adc_i2c_1 10>, <&adc_i2c_1 11>,
345 <&adc_i2c_1 12>, <&adc_i2c_1 13>,
346 <&adc_i2c_1 14>, <&adc_i2c_1 15>,
347 <&adc0 0>, <&adc0 1>,
348 <&adc0 2>;
349 };
350};
351
352&mdio0 {
353 status = "okay";
354
355 ethphy0: ethernet-phy@0 {
356 compatible = "ethernet-phy-ieee802.3-c22";
357 reg = <0>;
358 };
359};
360
361&mac0 {
362 status = "okay";
363
364 phy-mode = "rgmii";
365 phy-handle = <&ethphy0>;
366
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_rgmii1_default>;
369};
370
371&mac3 {
372 status = "okay";
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_rmii4_default>;
375 clock-names = "MACCLK", "RCLK";
376 use-ncsi;
377};
378
379&fmc {
380 status = "okay";
381 flash@0 {
382 status = "okay";
383 m25p,fast-read;
384 label = "bmc";
385 spi-max-frequency = <50000000>;
386#include "openbmc-flash-layout-64.dtsi"
387 };
388
389 flash@1 {
390 status = "okay";
391 m25p,fast-read;
392 label = "alt-bmc";
393 spi-max-frequency = <50000000>;
394#include "openbmc-flash-layout-64-alt.dtsi"
395 };
396};
397
398&spi1 {
399 status = "okay";
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_spi1_default>;
402
403 flash@0 {
404 status = "okay";
405 m25p,fast-read;
406 label = "pnor";
407 spi-max-frequency = <20000000>;
408 };
409};
410
411&uart1 {
412 status = "okay";
413};
414
415&uart2 {
416 status = "okay";
417};
418
419&uart3 {
420 status = "okay";
421};
422
423&uart4 {
424 status = "okay";
425};
426
427&uart8 {
428 status = "okay";
429};
430
431&uart9 {
432 status = "okay";
433};
434
435&i2c0 {
436 status = "okay";
437
438 temperature-sensor@2e {
439 compatible = "adi,adt7490";
440 reg = <0x2e>;
441 };
442};
443
444&i2c1 {
445 status = "okay";
446};
447
448&i2c2 {
449 status = "okay";
450
451 psu@58 {
452 compatible = "pmbus";
453 reg = <0x58>;
454 };
455
456 psu@59 {
457 compatible = "pmbus";
458 reg = <0x59>;
459 };
460};
461
462&i2c3 {
463 status = "okay";
464 bus-frequency = <1000000>;
465 multi-master;
466 mctp-controller;
467
468 mctp@10 {
469 compatible = "mctp-i2c-controller";
470 reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
471 };
472};
473
474&i2c4 {
475 status = "okay";
476
477 adc_i2c_0: adc@14 {
478 compatible = "lltc,ltc2497";
479 reg = <0x14>;
480 vref-supply = <&voltage_mon_reg>;
481 #io-channel-cells = <1>;
482 };
483
484 adc_i2c_1: adc@16 {
485 compatible = "lltc,ltc2497";
486 reg = <0x16>;
487 vref-supply = <&voltage_mon_reg>;
488 #io-channel-cells = <1>;
489 };
490
491 eeprom@50 {
492 compatible = "atmel,24c64";
493 reg = <0x50>;
494 pagesize = <32>;
495 };
496
497 i2c-mux@70 {
498 compatible = "nxp,pca9545";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 reg = <0x70>;
502 i2c-mux-idle-disconnect;
503
504 i2c4_bus70_chn0: i2c@0 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 reg = <0x0>;
508
509 outlet_temp1: temperature-sensor@48 {
510 compatible = "ti,tmp75";
511 reg = <0x48>;
512 };
513 psu1_inlet_temp2: temperature-sensor@49 {
514 compatible = "ti,tmp75";
515 reg = <0x49>;
516 };
517 };
518
519 i2c4_bus70_chn1: i2c@1 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 reg = <0x1>;
523
524 pcie_zone_temp1: temperature-sensor@48 {
525 compatible = "ti,tmp75";
526 reg = <0x48>;
527 };
528 psu0_inlet_temp2: temperature-sensor@49 {
529 compatible = "ti,tmp75";
530 reg = <0x49>;
531 };
532 };
533
534 i2c4_bus70_chn2: i2c@2 {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 reg = <0x2>;
538
539 pcie_zone_temp2: temperature-sensor@48 {
540 compatible = "ti,tmp75";
541 reg = <0x48>;
542 };
543 outlet_temp2: temperature-sensor@49 {
544 compatible = "ti,tmp75";
545 reg = <0x49>;
546 };
547 };
548
549 i2c4_bus70_chn3: i2c@3 {
550 #address-cells = <1>;
551 #size-cells = <0>;
552 reg = <0x3>;
553
554 mb_inlet_temp1: temperature-sensor@7c {
555 compatible = "microchip,emc1413";
556 reg = <0x7c>;
557 };
558 mb_inlet_temp2: temperature-sensor@4c {
559 compatible = "microchip,emc1413";
560 reg = <0x4c>;
561 };
562 };
563 };
564};
565
566&i2c5 {
567 status = "okay";
568
569 i2c-mux@70 {
570 compatible = "nxp,pca9548";
571 #address-cells = <1>;
572 #size-cells = <0>;
573 reg = <0x70>;
574 i2c-mux-idle-disconnect;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]575
576 ocpslot_0: i2c@0 {
577 #address-cells = <1>;
578 #size-cells = <0>;
579 reg = <0x0>;
580
581 ocpslot_0_temp: temperature-sensor@1f {
582 compatible = "ti,tmp421";
583 reg = <0x1f>;
584 };
585 };
586
587 ocpslot_1: i2c@1 {
588 #address-cells = <1>;
589 #size-cells = <0>;
590 reg = <0x1>;
591
592 ocpslot_1_temp: temperature-sensor@1f {
593 compatible = "ti,tmp421";
594 reg = <0x1f>;
595 };
596 };
597
598 i2c_riser0: i2c@2 {
599 #address-cells = <1>;
600 #size-cells = <0>;
601 reg = <0x2>;
602
603 i2c-mux@72 {
604 compatible = "nxp,pca9546";
605 #address-cells = <1>;
606 #size-cells = <0>;
607 reg = <0x72>;
608 i2c-mux-idle-disconnect;
609
610 i2c_riser0_chn_0: i2c@0 {
611 #address-cells = <1>;
612 #size-cells = <0>;
613 reg = <0x0>;
614
615 eeprom@50 {
616 compatible = "atmel,24c02";
617 reg = <0x50>;
618 pagesize = <16>;
619 };
620 };
621 };
622 };
623
624 i2c_riser1: i2c@3 {
625 #address-cells = <1>;
626 #size-cells = <0>;
627 reg = <0x3>;
628
629 i2c-mux@72 {
630 compatible = "nxp,pca9546";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 reg = <0x72>;
634 i2c-mux-idle-disconnect;
635
636 i2c_riser1_chn_0: i2c@0 {
637 #address-cells = <1>;
638 #size-cells = <0>;
639 reg = <0x0>;
640
641 eeprom@50 {
642 compatible = "atmel,24c02";
643 reg = <0x50>;
644 pagesize = <16>;
645 };
646 };
647 };
648 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]649 };
650};
651
652&i2c6 {
653 status = "okay";
654 rtc@51 {
655 compatible = "nxp,pcf85063a";
656 reg = <0x51>;
657 };
658};
659
660&i2c7 {
661 status = "okay";
662};
663
664&i2c8 {
665 status = "okay";
666
667 temperature-sensor@48 {
668 compatible = "ti,tmp112";
669 reg = <0x48>;
670 };
671
672 gpio@77 {
673 compatible = "nxp,pca9539";
674 reg = <0x77>;
675 gpio-controller;
676 #address-cells = <1>;
677 #size-cells = <0>;
678 #gpio-cells = <2>;
679
680 bmc-ocp0-en-hog {
681 gpio-hog;
682 gpios = <7 GPIO_ACTIVE_LOW>;
683 output-high;
684 line-name = "bmc-ocp0-en-n";
685 };
686 };
687};
688
689&i2c9 {
690 status = "okay";
691 i2c-mux@70 {
692 compatible = "nxp,pca9548";
693 #address-cells = <1>;
694 #size-cells = <0>;
695 reg = <0x70>;
696 i2c-mux-idle-disconnect;
697
698 backplane_1: i2c@0 {
699 #address-cells = <1>;
700 #size-cells = <0>;
701 reg = <0x0>;
702
703 eeprom@50 {
704 compatible = "atmel,24c64";
705 reg = <0x50>;
706 pagesize = <32>;
707 };
708
709 i2c-mux@71 {
710 compatible = "nxp,pca9548";
711 #address-cells = <1>;
712 #size-cells = <0>;
713 reg = <0x71>;
714 i2c-mux-idle-disconnect;
715
716 nvmeslot_8: i2c@0 {
717 #address-cells = <1>;
718 #size-cells = <0>;
719 reg = <0x0>;
720 };
721 nvmeslot_9: i2c@1 {
722 #address-cells = <1>;
723 #size-cells = <0>;
724 reg = <0x1>;
725 };
726 nvmeslot_10: i2c@2 {
727 #address-cells = <1>;
728 #size-cells = <0>;
729 reg = <0x2>;
730 };
731 nvmeslot_11: i2c@3 {
732 #address-cells = <1>;
733 #size-cells = <0>;
734 reg = <0x3>;
735 };
736 nvmeslot_12: i2c@4 {
737 #address-cells = <1>;
738 #size-cells = <0>;
739 reg = <0x4>;
740 };
741 nvmeslot_13: i2c@5 {
742 #address-cells = <1>;
743 #size-cells = <0>;
744 reg = <0x5>;
745 };
746 nvmeslot_14: i2c@6 {
747 #address-cells = <1>;
748 #size-cells = <0>;
749 reg = <0x6>;
750 };
751 nvmeslot_15: i2c@7 {
752 #address-cells = <1>;
753 #size-cells = <0>;
754 reg = <0x7>;
755 };
756 };
757
758 tmp432@4c {
759 compatible = "ti,tmp75";
760 reg = <0x4c>;
761 };
762 };
763
764 backplane_2: i2c@2 {
765 #address-cells = <1>;
766 #size-cells = <0>;
767 reg = <0x2>;
768
769 eeprom@50 {
770 compatible = "atmel,24c64";
771 reg = <0x50>;
772 pagesize = <32>;
773 };
774
775 i2c-mux@71 {
776 compatible = "nxp,pca9548";
777 #address-cells = <1>;
778 #size-cells = <0>;
779 reg = <0x71>;
780 i2c-mux-idle-disconnect;
781
782 nvmeslot_16: i2c@0 {
783 #address-cells = <1>;
784 #size-cells = <0>;
785 reg = <0x0>;
786 };
787 nvmeslot_17: i2c@1 {
788 #address-cells = <1>;
789 #size-cells = <0>;
790 reg = <0x1>;
791 };
792 nvmeslot_18: i2c@2 {
793 #address-cells = <1>;
794 #size-cells = <0>;
795 reg = <0x2>;
796 };
797 nvmeslot_19: i2c@3 {
798 #address-cells = <1>;
799 #size-cells = <0>;
800 reg = <0x3>;
801 };
802 nvmeslot_20: i2c@4 {
803 #address-cells = <1>;
804 #size-cells = <0>;
805 reg = <0x4>;
806 };
807 nvmeslot_21: i2c@5 {
808 #address-cells = <1>;
809 #size-cells = <0>;
810 reg = <0x5>;
811 };
812 nvmeslot_22: i2c@6 {
813 #address-cells = <1>;
814 #size-cells = <0>;
815 reg = <0x6>;
816 };
817 nvmeslot_23: i2c@7 {
818 #address-cells = <1>;
819 #size-cells = <0>;
820 reg = <0x7>;
821 };
822 };
823
824 tmp432@4c {
825 compatible = "ti,tmp75";
826 reg = <0x4c>;
827 };
828 };
829
830 backplane_0: i2c@4 {
831 #address-cells = <1>;
832 #size-cells = <0>;
833 reg = <0x4>;
834
835 eeprom@50 {
836 compatible = "atmel,24c64";
837 reg = <0x50>;
838 pagesize = <32>;
839 };
840
841 i2c-mux@71 {
842 compatible = "nxp,pca9548";
843 #address-cells = <1>;
844 #size-cells = <0>;
845 reg = <0x71>;
846 i2c-mux-idle-disconnect;
847
848 nvmeslot_0: i2c@0 {
849 #address-cells = <1>;
850 #size-cells = <0>;
851 reg = <0x0>;
852 };
853 nvmeslot_1: i2c@1 {
854 #address-cells = <1>;
855 #size-cells = <0>;
856 reg = <0x1>;
857 };
858 nvmeslot_2: i2c@2 {
859 #address-cells = <1>;
860 #size-cells = <0>;
861 reg = <0x2>;
862 };
863 nvmeslot_3: i2c@3 {
864 #address-cells = <1>;
865 #size-cells = <0>;
866 reg = <0x3>;
867 };
868 nvmeslot_4: i2c@4 {
869 #address-cells = <1>;
870 #size-cells = <0>;
871 reg = <0x4>;
872 };
873 nvmeslot_5: i2c@5 {
874 #address-cells = <1>;
875 #size-cells = <0>;
876 reg = <0x5>;
877 };
878 nvmeslot_6: i2c@6 {
879 #address-cells = <1>;
880 #size-cells = <0>;
881 reg = <0x6>;
882 };
883 nvmeslot_7: i2c@7 {
884 #address-cells = <1>;
885 #size-cells = <0>;
886 reg = <0x7>;
887 };
888 };
889
890 tmp432@4c {
891 compatible = "ti,tmp75";
892 reg = <0x4c>;
893 };
894 };
895
896 i2c@7 {
897 #address-cells = <1>;
898 #size-cells = <0>;
899 reg = <0x7>;
900
901 i2c-mux@71 {
902 compatible = "nxp,pca9546";
903 #address-cells = <1>;
904 #size-cells = <0>;
905 reg = <0x71>;
906 i2c-mux-idle-disconnect;
907
908 nvme_m2_0: i2c@0 {
909 #address-cells = <1>;
910 #size-cells = <0>;
911 reg = <0x0>;
912 };
913
914 nvme_m2_1: i2c@1 {
915 #address-cells = <1>;
916 #size-cells = <0>;
917 reg = <0x1>;
918 };
919 };
920 };
921 };
922};
923
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]924&i2c10 {
925 status = "okay";
926};
927
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]928&i2c11 {
929 status = "okay";
930 ssif-bmc@10 {
931 compatible = "ssif-bmc";
932 reg = <0x10>;
933 };
934};
935
936&i2c14 {
937 status = "okay";
938 eeprom@50 {
939 compatible = "atmel,24c64";
940 reg = <0x50>;
941 pagesize = <32>;
942 };
943
944 bmc_ast2600_cpu: temperature-sensor@35 {
945 compatible = "ti,tmp175";
946 reg = <0x35>;
947 };
948};
949
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]950&i2c15 {
951 status = "okay";
952 gpio_expander1: gpio-expander@22 {
953 compatible = "nxp,pca9535";
954 reg = <0x22>;
955 gpio-controller;
956 #gpio-cells = <2>;
957 gpio-line-names =
958 "fan-fault","psu-fault",
959 "","",
960 "","",
961 "","",
962 "","",
963 "","",
964 "","",
965 "","";
966 };
967};
968
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]969&adc0 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]970 status = "okay";
971
972 pinctrl-names = "default";
973 pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
974 &pinctrl_adc2_default>;
975};
976
977&vhub {
978 status = "okay";
979};
980
981&video {
982 status = "okay";
983 memory-region = <&video_engine_memory>;
984};
985
986&gpio0 {
987 gpio-line-names =
988 /*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n",
989 /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","",
990 /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","bmc-debug-mode","",
991 "irq-n","","vrd-sel","spd-sel",
992 /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n",
993 "","bmc-ncsi-txen","","",
994 /*E0-E7*/ "","eth-phy-int-n","clk50m-bmc-ncsi","","","","","",
995 /*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control",
996 "cpu-bios-recover","s0-heartbeat","hs-csout-prochot",
997 "s0-vr-hot-n","s1-vr-hot-n",
998 /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","",
999 /*H0-H7*/ "jtag-program-sel","fpga-program-b","wd-disable-n",
1000 "power-chassis-good","","","","",
1001 /*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable",
1002 /*J0-J7*/ "","","","","","","","",
1003 /*K0-K7*/ "","","","","","","","",
1004 /*L0-L7*/ "","","","","","","","",
1005 /*M0-M7*/ "","s0-ddr-save","soc-spi-nor-access","presence-cpu0",
1006 "s0-rtc-lock","","","",
1007 /*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb",
1008 "jtag-dbgr-prsnt-n","s1-heartbeat","","",
1009 /*O0-O7*/ "","","","","","","","",
1010 /*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","",
1011 "led-fault","cpld-user-mode","jtag-srst-n","led-bmc-hb",
1012 /*Q0-Q7*/ "","","","","","","","",
1013 /*R0-R7*/ "","","","","","","","",
1014 /*S0-S7*/ "","","identify-button","led-identify",
1015 "s1-ddr-save","spi-nor-access","host0-ready","presence-cpu1",
1016 /*T0-T7*/ "","","","","","","","",
1017 /*U0-U7*/ "","","","","","","","",
1018 /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
1019 "host0-reboot-ack-n","s0-fw-boot-ok","host0-shd-req-n",
1020 "host0-shd-ack-n","s0-overtemp-n",
1021 /*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","s1-pcp-pgood",
1022 "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel",
1023 /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok",
1024 "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n",
1025 "s1-overtemp-n","cpld-s1-spi-auth-fail-n",
1026 /*Y0-Y7*/ "","","","","","","","host0-special-boot",
1027 /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","","";
1028
1029 ocp-aux-pwren-hog {
1030 gpio-hog;
1031 gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
1032 output-high;
1033 line-name = "ocp-aux-pwren";
1034 };
1035};
1036
1037&gpio1 {
1038 gpio-line-names =
1039 /*18A0-18A7*/ "","","","","","","","",
1040 /*18B0-18B7*/ "","","","","","","s0-soc-pgood","",
1041 /*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1",
1042 "uart3-mode0","uart3-mode1","uart4-mode0","uart4-mode1",
1043 /*18D0-18D7*/ "","","","","","","","",
1044 /*18E0-18E3*/ "","","","";
1045};