Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: BSD-3-Clause AND GPL-2.0 |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 2 | /* |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 3 | * Clock and reset drivers for Qualcomm platforms Global Clock |
| 4 | * Controller (GCC). |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 5 | * |
| 6 | * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 7 | * (C) Copyright 2020 Sartura Ltd. (reset driver) |
| 8 | * Author: Robert Marko <robert.marko@sartura.hr> |
| 9 | * (C) Copyright 2022 Linaro Ltd. (reset driver) |
| 10 | * Author: Sumit Garg <sumit.garg@linaro.org> |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 11 | * |
| 12 | * Based on Little Kernel driver, simplified |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <clk-uclass.h> |
| 17 | #include <dm.h> |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 18 | #include <dm/device-internal.h> |
| 19 | #include <dm/lists.h> |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 20 | #include <errno.h> |
| 21 | #include <asm/io.h> |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 22 | #include <linux/bug.h> |
| 23 | #include <linux/delay.h> |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 24 | #include <linux/bitops.h> |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 25 | #include <reset-uclass.h> |
| 26 | |
Caleb Connolly | 878b26a | 2023-11-07 12:40:59 +0000 | [diff] [blame] | 27 | #include "clock-qcom.h" |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 28 | |
| 29 | /* CBCR register fields */ |
| 30 | #define CBCR_BRANCH_ENABLE_BIT BIT(0) |
| 31 | #define CBCR_BRANCH_OFF_BIT BIT(31) |
| 32 | |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 33 | /* Enable clock controlled by CBC soft macro */ |
| 34 | void clk_enable_cbc(phys_addr_t cbcr) |
| 35 | { |
| 36 | setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT); |
| 37 | |
| 38 | while (readl(cbcr) & CBCR_BRANCH_OFF_BIT) |
| 39 | ; |
| 40 | } |
| 41 | |
Ramon Fried | ae29977 | 2018-05-16 12:13:39 +0300 | [diff] [blame] | 42 | void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 43 | { |
| 44 | if (readl(base + gpll0->status) & gpll0->status_bit) |
| 45 | return; /* clock already enabled */ |
| 46 | |
| 47 | setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); |
| 48 | |
| 49 | while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) |
| 50 | ; |
| 51 | } |
| 52 | |
Ramon Fried | ae29977 | 2018-05-16 12:13:39 +0300 | [diff] [blame] | 53 | #define BRANCH_ON_VAL (0) |
| 54 | #define BRANCH_NOC_FSM_ON_VAL BIT(29) |
| 55 | #define BRANCH_CHECK_MASK GENMASK(31, 28) |
| 56 | |
| 57 | void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) |
| 58 | { |
| 59 | u32 val; |
| 60 | |
| 61 | setbits_le32(base + vclk->ena_vote, vclk->vote_bit); |
| 62 | do { |
| 63 | val = readl(base + vclk->cbcr_reg); |
| 64 | val &= BRANCH_CHECK_MASK; |
| 65 | } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); |
| 66 | } |
| 67 | |
Sheep Sun | 49fee7b | 2021-06-20 10:34:35 +0800 | [diff] [blame] | 68 | #define APPS_CMD_RCGR_UPDATE BIT(0) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 69 | |
Sheep Sun | 49fee7b | 2021-06-20 10:34:35 +0800 | [diff] [blame] | 70 | /* Update clock command via CMD_RCGR */ |
| 71 | void clk_bcr_update(phys_addr_t apps_cmd_rcgr) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 72 | { |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 73 | u32 count; |
Sheep Sun | 49fee7b | 2021-06-20 10:34:35 +0800 | [diff] [blame] | 74 | setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 75 | |
| 76 | /* Wait for frequency to be updated. */ |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 77 | for (count = 0; count < 50000; count++) { |
| 78 | if (!(readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)) |
| 79 | break; |
| 80 | udelay(1); |
| 81 | } |
| 82 | WARN(count == 50000, "WARNING: RCG @ %#llx [%#010x] stuck at off\n", |
| 83 | apps_cmd_rcgr, readl(apps_cmd_rcgr)); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 84 | } |
| 85 | |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 86 | #define CFG_SRC_DIV_MASK 0b11111 |
| 87 | #define CFG_SRC_SEL_SHIFT 8 |
| 88 | #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT) |
| 89 | #define CFG_MODE_SHIFT 12 |
| 90 | #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) |
| 91 | #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) |
| 92 | #define CFG_HW_CLK_CTRL_MASK BIT(20) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 93 | |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 94 | /* |
| 95 | * root set rate for clocks with half integer and MND divider |
| 96 | * div should be pre-calculated ((div * 2) - 1) |
| 97 | */ |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 98 | void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, |
Caleb Connolly | fbacc67 | 2023-11-07 12:41:04 +0000 | [diff] [blame] | 99 | int div, int m, int n, int source, u8 mnd_width) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 100 | { |
| 101 | u32 cfg; |
| 102 | /* M value for MND divider. */ |
| 103 | u32 m_val = m; |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 104 | u32 n_minus_m = n - m; |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 105 | /* NOT(N-M) value for MND divider. */ |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 106 | u32 n_val = ~n_minus_m * !!(n); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 107 | /* NOT 2D value for MND divider. */ |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 108 | u32 d_val = ~(clamp_t(u32, n, m, n_minus_m)); |
Caleb Connolly | fbacc67 | 2023-11-07 12:41:04 +0000 | [diff] [blame] | 109 | u32 mask = BIT(mnd_width) - 1; |
| 110 | |
| 111 | debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 112 | |
| 113 | /* Program MND values */ |
Caleb Connolly | fbacc67 | 2023-11-07 12:41:04 +0000 | [diff] [blame] | 114 | writel(m_val & mask, base + regs->M); |
| 115 | writel(n_val & mask, base + regs->N); |
| 116 | writel(d_val & mask, base + regs->D); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 117 | |
| 118 | /* setup src select and divider */ |
| 119 | cfg = readl(base + regs->cfg_rcgr); |
Volodymyr Babchuk | 8eca261 | 2024-03-11 21:33:45 +0000 | [diff] [blame^] | 120 | cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | |
| 121 | CFG_SRC_DIV_MASK); |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 122 | cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 123 | |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 124 | if (div) |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 125 | cfg |= div & CFG_SRC_DIV_MASK; |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 126 | |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 127 | if (n && n != m) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 128 | cfg |= CFG_MODE_DUAL_EDGE; |
| 129 | |
| 130 | writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ |
| 131 | |
| 132 | /* Inform h/w to start using the new config. */ |
| 133 | clk_bcr_update(base + regs->cmd_rcgr); |
| 134 | } |
| 135 | |
Sumit Garg | a3e804d | 2023-02-01 19:28:57 +0530 | [diff] [blame] | 136 | /* root set rate for clocks with half integer and mnd_width=0 */ |
| 137 | void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, |
| 138 | int source) |
| 139 | { |
| 140 | u32 cfg; |
| 141 | |
| 142 | /* setup src select and divider */ |
| 143 | cfg = readl(base + regs->cfg_rcgr); |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 144 | cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); |
Sumit Garg | a3e804d | 2023-02-01 19:28:57 +0530 | [diff] [blame] | 145 | cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ |
| 146 | |
| 147 | /* |
| 148 | * Set the divider; HW permits fraction dividers (+0.5), but |
| 149 | * for simplicity, we will support integers only |
| 150 | */ |
| 151 | if (div) |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 152 | cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK; |
Sumit Garg | a3e804d | 2023-02-01 19:28:57 +0530 | [diff] [blame] | 153 | |
| 154 | writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ |
| 155 | |
| 156 | /* Inform h/w to start using the new config. */ |
| 157 | clk_bcr_update(base + regs->cmd_rcgr); |
| 158 | } |
| 159 | |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 160 | const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) |
| 161 | { |
| 162 | if (!f) |
| 163 | return NULL; |
| 164 | |
| 165 | if (!f->freq) |
| 166 | return f; |
| 167 | |
| 168 | for (; f->freq; f++) |
| 169 | if (rate <= f->freq) |
| 170 | return f; |
| 171 | |
| 172 | /* Default to our fastest rate */ |
| 173 | return f - 1; |
| 174 | } |
| 175 | |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 176 | static int msm_clk_probe(struct udevice *dev) |
| 177 | { |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 178 | struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 179 | struct msm_clk_priv *priv = dev_get_priv(dev); |
| 180 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 181 | priv->base = dev_read_addr(dev); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 182 | if (priv->base == FDT_ADDR_T_NONE) |
| 183 | return -EINVAL; |
| 184 | |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 185 | priv->data = data; |
| 186 | |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 187 | return 0; |
| 188 | } |
| 189 | |
| 190 | static ulong msm_clk_set_rate(struct clk *clk, ulong rate) |
| 191 | { |
Caleb Connolly | 10a0abb | 2023-11-07 12:41:03 +0000 | [diff] [blame] | 192 | struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev); |
| 193 | |
| 194 | if (data->set_rate) |
| 195 | return data->set_rate(clk, rate); |
| 196 | |
| 197 | return 0; |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 198 | } |
| 199 | |
Sumit Garg | 1d1ca6e | 2022-08-04 19:57:14 +0530 | [diff] [blame] | 200 | static int msm_clk_enable(struct clk *clk) |
| 201 | { |
Caleb Connolly | 10a0abb | 2023-11-07 12:41:03 +0000 | [diff] [blame] | 202 | struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev); |
| 203 | |
| 204 | if (data->enable) |
| 205 | return data->enable(clk); |
| 206 | |
| 207 | return 0; |
Sumit Garg | 1d1ca6e | 2022-08-04 19:57:14 +0530 | [diff] [blame] | 208 | } |
| 209 | |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 210 | static struct clk_ops msm_clk_ops = { |
| 211 | .set_rate = msm_clk_set_rate, |
Sumit Garg | 1d1ca6e | 2022-08-04 19:57:14 +0530 | [diff] [blame] | 212 | .enable = msm_clk_enable, |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 213 | }; |
| 214 | |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 215 | U_BOOT_DRIVER(qcom_clk) = { |
| 216 | .name = "qcom_clk", |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 217 | .id = UCLASS_CLK, |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 218 | .ops = &msm_clk_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 219 | .priv_auto = sizeof(struct msm_clk_priv), |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 220 | .probe = msm_clk_probe, |
| 221 | }; |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 222 | |
| 223 | int qcom_cc_bind(struct udevice *parent) |
| 224 | { |
| 225 | struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent); |
| 226 | struct udevice *clkdev, *rstdev; |
| 227 | struct driver *drv; |
| 228 | int ret; |
| 229 | |
| 230 | /* Get a handle to the common clk handler */ |
| 231 | drv = lists_driver_lookup_name("qcom_clk"); |
| 232 | if (!drv) |
| 233 | return -ENOENT; |
| 234 | |
| 235 | /* Register the clock controller */ |
| 236 | ret = device_bind_with_driver_data(parent, drv, "qcom_clk", (ulong)data, |
| 237 | dev_ofnode(parent), &clkdev); |
| 238 | if (ret) |
| 239 | return ret; |
| 240 | |
| 241 | /* Bail out early if resets are not specified for this platform */ |
| 242 | if (!data->resets) |
| 243 | return ret; |
| 244 | |
| 245 | /* Get a handle to the common reset handler */ |
| 246 | drv = lists_driver_lookup_name("qcom_reset"); |
| 247 | if (!drv) |
| 248 | return -ENOENT; |
| 249 | |
| 250 | /* Register the reset controller */ |
| 251 | ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data, |
| 252 | dev_ofnode(parent), &rstdev); |
| 253 | if (ret) |
| 254 | device_unbind(clkdev); |
| 255 | |
| 256 | return ret; |
| 257 | } |
| 258 | |
| 259 | static int qcom_reset_set(struct reset_ctl *rst, bool assert) |
| 260 | { |
| 261 | struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(rst->dev); |
| 262 | void __iomem *base = dev_get_priv(rst->dev); |
| 263 | const struct qcom_reset_map *map; |
| 264 | u32 value; |
| 265 | |
| 266 | map = &data->resets[rst->id]; |
| 267 | |
| 268 | value = readl(base + map->reg); |
| 269 | |
| 270 | if (assert) |
| 271 | value |= BIT(map->bit); |
| 272 | else |
| 273 | value &= ~BIT(map->bit); |
| 274 | |
| 275 | writel(value, base + map->reg); |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | static int qcom_reset_assert(struct reset_ctl *rst) |
| 281 | { |
| 282 | return qcom_reset_set(rst, true); |
| 283 | } |
| 284 | |
| 285 | static int qcom_reset_deassert(struct reset_ctl *rst) |
| 286 | { |
| 287 | return qcom_reset_set(rst, false); |
| 288 | } |
| 289 | |
| 290 | static const struct reset_ops qcom_reset_ops = { |
| 291 | .rst_assert = qcom_reset_assert, |
| 292 | .rst_deassert = qcom_reset_deassert, |
| 293 | }; |
| 294 | |
| 295 | static int qcom_reset_probe(struct udevice *dev) |
| 296 | { |
| 297 | /* Set our priv pointer to the base address */ |
| 298 | dev_set_priv(dev, (void *)dev_read_addr(dev)); |
| 299 | |
| 300 | return 0; |
| 301 | } |
| 302 | |
| 303 | U_BOOT_DRIVER(qcom_reset) = { |
| 304 | .name = "qcom_reset", |
| 305 | .id = UCLASS_RESET, |
| 306 | .ops = &qcom_reset_ops, |
| 307 | .probe = qcom_reset_probe, |
| 308 | }; |