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Michael Jones8ce85da2011-11-04 13:53:44 -04001/*
2 * MATRIX VISION GmbH mvBlueLYNX-X
3 *
4 * Derived from omap3_beagle.h:
5 * (C) Copyright 2006-2008
6 * Texas Instruments.
7 * Richard Woodruff <r-woodruff2@ti.com>
8 * Syed Mohammed Khasim <x0khasim@ti.com>
9 *
10 * Configuration settings for the TI OMAP3530 Beagle board.
11 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
Michael Jones8ce85da2011-11-04 13:53:44 -040013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 */
Michael Jones8ce85da2011-11-04 13:53:44 -040021#define CONFIG_OMAP 1 /* in a TI OMAP core */
Michael Jones8ce85da2011-11-04 13:53:44 -040022#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
23#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
Marek Vasutaede1882012-07-21 05:02:23 +000024#define CONFIG_OMAP_GPIO
Lokesh Vutla56055052013-07-30 11:36:30 +053025#define CONFIG_OMAP_COMMON
Nishanth Menon3e46e3e2015-03-09 17:12:08 -050026/* Common ARM Erratas */
27#define CONFIG_ARM_ERRATA_454179
28#define CONFIG_ARM_ERRATA_430973
29#define CONFIG_ARM_ERRATA_621766
Michael Jones8ce85da2011-11-04 13:53:44 -040030
31#define CONFIG_SDRC /* The chip has SDRC controller */
32
33#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menonfa96c962015-03-09 17:12:04 -050034#include <asm/arch/omap.h>
Michael Jones8ce85da2011-11-04 13:53:44 -040035
36/*
37 * Display CPU and Board information
38 */
39#define CONFIG_DISPLAY_CPUINFO 1
40#define CONFIG_DISPLAY_BOARDINFO 1
41
42/* Clock Defines */
43#define V_OSCK 26000000 /* Clock output from T2 */
44#define V_SCLK (V_OSCK >> 1)
45
Michael Jones8ce85da2011-11-04 13:53:44 -040046#define CONFIG_MISC_INIT_R
47
48#define CONFIG_OF_LIBFDT 1
49
50#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
51#define CONFIG_SETUP_MEMORY_TAGS 1
52#define CONFIG_INITRD_TAG 1
53#define CONFIG_REVISION_TAG 1
54#define CONFIG_SERIAL_TAG 1
55
56/*
57 * Size of malloc() pool
58 */
59#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
60 /* Sector */
61#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
62
63/*
64 * Hardware drivers
65 */
66
67/*
68 * NS16550 Configuration
69 */
70#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
71
72#define CONFIG_SYS_NS16550
73#define CONFIG_SYS_NS16550_SERIAL
74#define CONFIG_SYS_NS16550_REG_SIZE (-4)
75#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
76
77/*
78 * select serial console configuration
79 */
Howard Grayef6b29e2013-02-07 23:53:35 +000080#define CONFIG_CONS_INDEX 1
81#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
82#define CONFIG_SERIAL1 1 /* UART1 */
Michael Jones8ce85da2011-11-04 13:53:44 -040083
84#define CONFIG_BAUDRATE 115200
85#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
86 115200}
87#define CONFIG_GENERIC_MMC 1
88#define CONFIG_MMC 1
89#define CONFIG_OMAP_HSMMC 1
90#define CONFIG_DOS_PARTITION 1
91
Howard Grayef6b29e2013-02-07 23:53:35 +000092/* silent console by default */
93#define CONFIG_SYS_DEVICE_NULLDEV 1
94#define CONFIG_SILENT_CONSOLE 1
95
Michael Jones8ce85da2011-11-04 13:53:44 -040096/* USB */
97#define CONFIG_MUSB_UDC 1
98#define CONFIG_USB_OMAP3 1
99#define CONFIG_TWL4030_USB 1
100
101/* USB device configuration */
102#define CONFIG_USB_DEVICE 1
103#define CONFIG_USB_TTY 1
104#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
105#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
106#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
107#define CONFIG_USBD_VENDORID 0x164c
108#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
109#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
110#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
111#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
112
113/* no FLASH available */
114#define CONFIG_SYS_NO_FLASH
115
116/* commands to include */
Michael Jones8ce85da2011-11-04 13:53:44 -0400117#define CONFIG_CMD_CACHE
118#define CONFIG_CMD_EXT2 /* EXT2 Support */
119#define CONFIG_CMD_FAT /* FAT support */
120#define CONFIG_CMD_I2C /* I2C serial bus support */
121#define CONFIG_CMD_MMC /* MMC support */
122#define CONFIG_CMD_EEPROM
Michael Jones8ce85da2011-11-04 13:53:44 -0400123#define CONFIG_CMD_DHCP
124#define CONFIG_CMD_PING
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530125#define CONFIG_CMD_FPGA_LOADMK
Michael Jones8ce85da2011-11-04 13:53:44 -0400126
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200127#define CONFIG_SYS_I2C
128#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
129#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
130#define CONFIG_SYS_I2C_OMAP34XX
Michael Jones8ce85da2011-11-04 13:53:44 -0400131
132/*
133 * TWL4030
134 */
135#define CONFIG_TWL4030_POWER 1
136
137/* Environment information */
138#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
Howard Grayef6b29e2013-02-07 23:53:35 +0000139#define CONFIG_BOOTDELAY 0
140#define CONFIG_ZERO_BOOTDELAY_CHECK
Michael Jones8ce85da2011-11-04 13:53:44 -0400141
142#define CONFIG_EXTRA_ENV_SETTINGS \
Howard Grayef6b29e2013-02-07 23:53:35 +0000143 "silent=true\0" \
Michael Jones8ce85da2011-11-04 13:53:44 -0400144 "loadaddr=0x82000000\0" \
145 "usbtty=cdc_acm\0" \
Howard Grayef6b29e2013-02-07 23:53:35 +0000146 "console=ttyO0,115200n8\0" \
Michael Jones8ce85da2011-11-04 13:53:44 -0400147 "mpurate=600\0" \
148 "vram=12M\0" \
149 "dvimode=1024x768-24@60\0" \
150 "defaultdisplay=dvi\0" \
Michael Jones284a2492013-02-07 23:53:36 +0000151 "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
152 "/lib/firmware/mvblx/${fpgafilename}; then " \
153 "fpga load 0 ${loadaddr} ${filesize}; " \
Michael Jones8ce85da2011-11-04 13:53:44 -0400154 "fi;\0" \
155 "mmcdev=0\0" \
156 "mmcroot=/dev/mmcblk0p2 rw\0" \
157 "mmcrootfstype=ext3 rootwait\0" \
158 "mmcargs=setenv bootargs console=${console} " \
159 "mpurate=${mpurate} " \
160 "vram=${vram} " \
161 "omapfb.mode=dvi:${dvimode} " \
162 "omapfb.debug=y " \
163 "omapdss.def_disp=${defaultdisplay} " \
164 "root=${mmcroot} " \
165 "rootfstype=${mmcrootfstype} " \
Michael Jones552613c2013-02-07 23:53:37 +0000166 "mvfw.fpgavers=${fpgavers} " \
Michael Jones8ce85da2011-11-04 13:53:44 -0400167 "${cmdline_suffix}\0" \
168 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
169 "importbootenv=echo Importing environment from mmc ...; " \
170 "env import -t $loadaddr $filesize\0" \
171 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
172 "mmcboot=echo Booting from mmc ...; " \
173 "run mmcargs; " \
174 "bootm ${loadaddr}\0" \
175 "mmcbootcmd= " \
176 "echo Trying mmc${mmcdev}; " \
177 "mmc dev ${mmcdev}; " \
178 "if mmc rescan; then " \
179 "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
180 "echo SD/MMC found on device ${mmcdev};" \
181 "if run loadbootenv; then " \
182 "echo Loading boot environment from mmc${mmcdev}; " \
183 "run importbootenv; " \
184 "fi;" \
185 "run loadfpga; " \
186 "if test -n $uenvcmd; then " \
187 "echo Running uenvcmd ...;" \
188 "run uenvcmd;" \
189 "fi;" \
190 "if run loaduimage; then " \
191 "run mmcboot; " \
192 "fi;" \
193 "fi\0"
194
195#define CONFIG_BOOTCOMMAND \
196 "setenv mmcdev 1;" \
197 "run mmcbootcmd || " \
198 "setenv mmcdev 0;" \
199 "run mmcbootcmd"
200
201
202#define CONFIG_AUTO_COMPLETE 1
203/*
204 * Miscellaneous configurable options
205 */
206#define CONFIG_SYS_LONGHELP /* undef to save memory */
207#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Michael Jones8ce85da2011-11-04 13:53:44 -0400208#define CONFIG_SYS_PROMPT "mvblx # "
209#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
210/* Print Buffer Size */
211#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
212 sizeof(CONFIG_SYS_PROMPT) + 16)
213#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
214/* Boot Argument Buffer Size */
215#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
216
217#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
218#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
219#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
220#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
221
222/* default load address */
223#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
224
225/*
226 * OMAP3 has 12 GP timers, they can be driven by the system clock
227 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
228 * This rate is divided by a local divisor.
229 */
230#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
231#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Michael Jones8ce85da2011-11-04 13:53:44 -0400232
233/*-----------------------------------------------------------------------
Michael Jones8ce85da2011-11-04 13:53:44 -0400234 * Physical Memory Map
235 */
236#define CONFIG_NR_DRAM_BANKS 1
237#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Michael Jones8ce85da2011-11-04 13:53:44 -0400238#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
239
Michael Jones8ce85da2011-11-04 13:53:44 -0400240#define CONFIG_ENV_IS_NOWHERE 1
241
242/*----------------------------------------------------------------------------
243 * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
244 *----------------------------------------------------------------------------
245 */
246#if defined(CONFIG_CMD_NET)
Michael Jones8ce85da2011-11-04 13:53:44 -0400247 #define CONFIG_SMC911X 1
248 #define CONFIG_SMC911X_32_BIT
249 #define CONFIG_SMC911X_BASE 0x2C000000
250#endif /* (CONFIG_CMD_NET) */
251
252#define CONFIG_FPGA_COUNT 1
Michal Simekb6b8aaa2013-05-01 18:05:56 +0200253#define CONFIG_FPGA
Michael Jones8ce85da2011-11-04 13:53:44 -0400254#define CONFIG_FPGA_ALTERA
255#define CONFIG_FPGA_CYCLON2
256#define CONFIG_SYS_FPGA_PROG_FEEDBACK
257#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
258
259#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
260#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
261#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
262#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
263#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
264#define CONFIG_ID_EEPROM
265#define CONFIG_SYS_EEPROM_BUS_NUM 2
266
267#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
268#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
269#define CONFIG_SYS_INIT_RAM_SIZE 0x800
270#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
271 CONFIG_SYS_INIT_RAM_SIZE - \
272 GENERATED_GBL_DATA_SIZE)
273
274#define CONFIG_OMAP3_SPI
275
Aneesh Vfa5c07a2011-11-21 23:38:59 +0000276#define CONFIG_SYS_CACHELINE_SIZE 64
277
Michael Jones8ce85da2011-11-04 13:53:44 -0400278#endif /* __CONFIG_H */