Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000-2002 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 5 | * |
| 6 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
| 7 | * Scott McNutt <smcnutt@psyent.com> |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <dm.h> |
| 12 | #include <errno.h> |
| 13 | #include <timer.h> |
| 14 | #include <asm/io.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 15 | #include <linux/bitops.h> |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 16 | |
Thomas Chou | 90b1d79 | 2015-10-31 20:54:16 +0800 | [diff] [blame] | 17 | /* control register */ |
| 18 | #define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */ |
| 19 | #define ALTERA_TIMER_START BIT(2) /* Start timer */ |
| 20 | #define ALTERA_TIMER_STOP BIT(3) /* Stop timer */ |
| 21 | |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 22 | struct altera_timer_regs { |
| 23 | u32 status; /* Timer status reg */ |
| 24 | u32 control; /* Timer control reg */ |
| 25 | u32 periodl; /* Timeout period low */ |
| 26 | u32 periodh; /* Timeout period high */ |
| 27 | u32 snapl; /* Snapshot low */ |
| 28 | u32 snaph; /* Snapshot high */ |
| 29 | }; |
| 30 | |
| 31 | struct altera_timer_platdata { |
| 32 | struct altera_timer_regs *regs; |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 33 | }; |
| 34 | |
Sean Anderson | 947fc2d | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 35 | static u64 altera_timer_get_count(struct udevice *dev) |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 36 | { |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 37 | struct altera_timer_platdata *plat = dev->plat; |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 38 | struct altera_timer_regs *const regs = plat->regs; |
| 39 | u32 val; |
| 40 | |
| 41 | /* Trigger update */ |
| 42 | writel(0x0, ®s->snapl); |
| 43 | |
| 44 | /* Read timer value */ |
| 45 | val = readl(®s->snapl) & 0xffff; |
| 46 | val |= (readl(®s->snaph) & 0xffff) << 16; |
Sean Anderson | 947fc2d | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 47 | return timer_conv_64(~val); |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | static int altera_timer_probe(struct udevice *dev) |
| 51 | { |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 52 | struct altera_timer_platdata *plat = dev->plat; |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 53 | struct altera_timer_regs *const regs = plat->regs; |
| 54 | |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 55 | writel(0, ®s->status); |
| 56 | writel(0, ®s->control); |
| 57 | writel(ALTERA_TIMER_STOP, ®s->control); |
| 58 | |
| 59 | writel(0xffff, ®s->periodl); |
| 60 | writel(0xffff, ®s->periodh); |
| 61 | writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, ®s->control); |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | static int altera_timer_ofdata_to_platdata(struct udevice *dev) |
| 67 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame^] | 68 | struct altera_timer_platdata *plat = dev_get_plat(dev); |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 69 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 70 | plat->regs = map_physmem(dev_read_addr(dev), |
Thomas Chou | d82a4d3 | 2015-11-14 11:15:31 +0800 | [diff] [blame] | 71 | sizeof(struct altera_timer_regs), |
| 72 | MAP_NOCACHE); |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | static const struct timer_ops altera_timer_ops = { |
| 78 | .get_count = altera_timer_get_count, |
| 79 | }; |
| 80 | |
| 81 | static const struct udevice_id altera_timer_ids[] = { |
Thomas Chou | 90b1d79 | 2015-10-31 20:54:16 +0800 | [diff] [blame] | 82 | { .compatible = "altr,timer-1.0" }, |
| 83 | {} |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 84 | }; |
| 85 | |
| 86 | U_BOOT_DRIVER(altera_timer) = { |
| 87 | .name = "altera_timer", |
| 88 | .id = UCLASS_TIMER, |
| 89 | .of_match = altera_timer_ids, |
| 90 | .ofdata_to_platdata = altera_timer_ofdata_to_platdata, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 91 | .plat_auto = sizeof(struct altera_timer_platdata), |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 92 | .probe = altera_timer_probe, |
| 93 | .ops = &altera_timer_ops, |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 94 | }; |