TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Configuation settings for the Freescale MCF5329 FireEngine board. |
| 3 | * |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * board/config.h - configuration options, board specific |
| 12 | */ |
| 13 | |
| 14 | #ifndef _M5329EVB_H |
| 15 | #define _M5329EVB_H |
| 16 | |
| 17 | /* |
| 18 | * High Level Configuration Options |
| 19 | * (easy to change) |
| 20 | */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 21 | |
TsiChungLiew | db0022d | 2007-08-05 03:19:10 -0500 | [diff] [blame] | 22 | #define CONFIG_MCFUART |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_UART_PORT (0) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 24 | #define CONFIG_BAUDRATE 115200 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 25 | |
| 26 | #undef CONFIG_WATCHDOG |
| 27 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ |
| 28 | |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 29 | /* Command line configuration */ |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 30 | #define CONFIG_CMD_CACHE |
| 31 | #define CONFIG_CMD_DATE |
| 32 | #define CONFIG_CMD_ELF |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 33 | #define CONFIG_CMD_I2C |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 34 | #define CONFIG_CMD_MII |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 35 | #define CONFIG_CMD_PING |
| 36 | #define CONFIG_CMD_REGINFO |
TsiChung | 6373c0c | 2007-07-10 15:45:43 -0500 | [diff] [blame] | 37 | |
stany MARCEL | 5ac9ea6 | 2011-10-19 00:17:13 +0800 | [diff] [blame] | 38 | #ifdef CONFIG_NANDFLASH_SIZE |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 39 | # define CONFIG_CMD_NAND |
TsiChungLiew | ec8468f | 2007-08-05 04:31:18 -0500 | [diff] [blame] | 40 | #endif |
| 41 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 42 | #define CONFIG_SYS_UNIFY_CACHE |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 43 | |
| 44 | #define CONFIG_MCFFEC |
| 45 | #ifdef CONFIG_MCFFEC |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 46 | # define CONFIG_MII 1 |
TsiChung Liew | b316245 | 2008-03-30 01:22:13 -0500 | [diff] [blame] | 47 | # define CONFIG_MII_INIT 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 48 | # define CONFIG_SYS_DISCOVER_PHY |
| 49 | # define CONFIG_SYS_RX_ETH_BUFFER 8 |
| 50 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 51 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | # define CONFIG_SYS_FEC0_PINMUX 0 |
| 53 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 54 | # define MCFFEC_TOUT_LOOP 50000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
| 56 | # ifndef CONFIG_SYS_DISCOVER_PHY |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 57 | # define FECDUPLEX FULL |
| 58 | # define FECSPEED _100BASET |
| 59 | # else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 60 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 61 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 62 | # endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 63 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 64 | #endif |
| 65 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 66 | #define CONFIG_MCFRTC |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 67 | #undef RTC_DEBUG |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 68 | |
| 69 | /* Timer */ |
| 70 | #define CONFIG_MCFTMR |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 71 | #undef CONFIG_MCFPIT |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 72 | |
TsiChungLiew | 876343b | 2007-08-05 04:11:20 -0500 | [diff] [blame] | 73 | /* I2C */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 74 | #define CONFIG_SYS_I2C |
| 75 | #define CONFIG_SYS_I2C_FSL |
| 76 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 |
| 77 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 78 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
TsiChungLiew | 876343b | 2007-08-05 04:11:20 -0500 | [diff] [blame] | 80 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 81 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 82 | #define CONFIG_UDP_CHECKSUM |
| 83 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 84 | #ifdef CONFIG_MCFFEC |
TsiChungLiew | 876343b | 2007-08-05 04:11:20 -0500 | [diff] [blame] | 85 | # define CONFIG_IPADDR 192.162.1.2 |
| 86 | # define CONFIG_NETMASK 255.255.255.0 |
| 87 | # define CONFIG_SERVERIP 192.162.1.1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 88 | # define CONFIG_GATEWAYIP 192.162.1.1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 89 | #endif /* FEC_ENET */ |
| 90 | |
| 91 | #define CONFIG_HOSTNAME M5329EVB |
| 92 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 93 | "netdev=eth0\0" \ |
| 94 | "loadaddr=40010000\0" \ |
| 95 | "u-boot=u-boot.bin\0" \ |
| 96 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 97 | "upd=run load; run prog\0" \ |
Jason Jin | ded4eb4 | 2011-08-19 10:10:40 +0800 | [diff] [blame] | 98 | "prog=prot off 0 3ffff;" \ |
| 99 | "era 0 3ffff;" \ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 100 | "cp.b ${loadaddr} 0 ${filesize};" \ |
| 101 | "save\0" \ |
| 102 | "" |
| 103 | |
TsiChungLiew | 876343b | 2007-08-05 04:11:20 -0500 | [diff] [blame] | 104 | #define CONFIG_PRAM 512 /* 512 KB */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | #define CONFIG_SYS_PROMPT "-> " |
| 106 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 107 | |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 108 | #ifdef CONFIG_CMD_KGDB |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 110 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 112 | #endif |
| 113 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 115 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 116 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 117 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 118 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_CLK 80000000 |
| 120 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 121 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_MBAR 0xFC000000 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 123 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) |
TsiChungLiew | ec8468f | 2007-08-05 04:31:18 -0500 | [diff] [blame] | 125 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 126 | /* |
| 127 | * Low Level Configuration Settings |
| 128 | * (address mappings, register initial values, etc.) |
| 129 | * You should know what you are doing if you make changes here. |
| 130 | */ |
| 131 | /*----------------------------------------------------------------------- |
| 132 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 133 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 135 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 137 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 139 | |
| 140 | /*----------------------------------------------------------------------- |
| 141 | * Start addresses for the final memory configuration |
| 142 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 143 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 144 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 145 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| 146 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ |
| 147 | #define CONFIG_SYS_SDRAM_CFG1 0x53722730 |
| 148 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 |
| 149 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 |
| 150 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 |
| 151 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 152 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
| 154 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 155 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
| 157 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 158 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 159 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
| 160 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 161 | |
| 162 | /* |
| 163 | * For booting Linux, the board info and command line data |
| 164 | * have to be in the first 8 MB of memory, since this is |
| 165 | * the maximum mapped by the Linux kernel during initialization ?? |
| 166 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
TsiChung Liew | 25a0063 | 2009-01-27 12:57:47 +0000 | [diff] [blame] | 168 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 169 | |
| 170 | /*----------------------------------------------------------------------- |
| 171 | * FLASH organization |
| 172 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_FLASH_CFI |
| 174 | #ifdef CONFIG_SYS_FLASH_CFI |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 175 | # define CONFIG_FLASH_CFI_DRIVER 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
| 177 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 178 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 179 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
| 180 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 181 | #endif |
| 182 | |
stany MARCEL | 5ac9ea6 | 2011-10-19 00:17:13 +0800 | [diff] [blame] | 183 | #ifdef CONFIG_NANDFLASH_SIZE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | # define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 185 | # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE |
| 186 | # define CONFIG_SYS_NAND_SIZE 1 |
| 187 | # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 188 | # define NAND_ALLOW_ERASE_ALL 1 |
| 189 | # define CONFIG_JFFS2_NAND 1 |
| 190 | # define CONFIG_JFFS2_DEV "nand0" |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 191 | # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 192 | # define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
TsiChungLiew | ec8468f | 2007-08-05 04:31:18 -0500 | [diff] [blame] | 193 | #endif |
| 194 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 196 | |
| 197 | /* Configuration for environment |
| 198 | * Environment is embedded in u-boot in the second sector of the flash |
| 199 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 200 | #define CONFIG_ENV_OFFSET 0x4000 |
| 201 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 202 | #define CONFIG_ENV_IS_IN_FLASH 1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 203 | |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 204 | #define LDS_BOARD_TEXT \ |
| 205 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 206 | common/env_embedded.o (.text*); |
| 207 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 208 | /*----------------------------------------------------------------------- |
| 209 | * Cache Configuration |
| 210 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 212 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 213 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 214 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 215 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 216 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 217 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
| 218 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ |
| 219 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 220 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 221 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ |
| 222 | CF_CACR_DCM_P) |
| 223 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 224 | /*----------------------------------------------------------------------- |
| 225 | * Chipselect bank definitions |
| 226 | */ |
| 227 | /* |
| 228 | * CS0 - NOR Flash 1, 2, 4, or 8MB |
| 229 | * CS1 - CompactFlash and registers |
| 230 | * CS2 - NAND Flash 16, 32, or 64MB |
| 231 | * CS3 - Available |
| 232 | * CS4 - Available |
| 233 | * CS5 - Available |
| 234 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 235 | #define CONFIG_SYS_CS0_BASE 0 |
| 236 | #define CONFIG_SYS_CS0_MASK 0x007f0001 |
| 237 | #define CONFIG_SYS_CS0_CTRL 0x00001fa0 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 238 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 239 | #define CONFIG_SYS_CS1_BASE 0x10000000 |
| 240 | #define CONFIG_SYS_CS1_MASK 0x001f0001 |
| 241 | #define CONFIG_SYS_CS1_CTRL 0x002A3780 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 242 | |
stany MARCEL | 5ac9ea6 | 2011-10-19 00:17:13 +0800 | [diff] [blame] | 243 | #ifdef CONFIG_NANDFLASH_SIZE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 244 | #define CONFIG_SYS_CS2_BASE 0x20000000 |
stany MARCEL | 5ac9ea6 | 2011-10-19 00:17:13 +0800 | [diff] [blame] | 245 | #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 246 | #define CONFIG_SYS_CS2_CTRL 0x00001f60 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 247 | #endif |
| 248 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 249 | #endif /* _M5329EVB_H */ |