| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_SOCFPGA=y |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_SPL_DM=y |
| 5 | CONFIG_DM_GPIO=y |
| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 6 | CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y |
| 7 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" |
| 8 | CONFIG_SPL=y |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 9 | CONFIG_SPL_STACK_R=y |
| 10 | CONFIG_SPL_STACK_R_ADDR=0x00800000 |
| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 11 | # CONFIG_CMD_IMLS is not set |
| 12 | # CONFIG_CMD_FLASH is not set |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 13 | CONFIG_SPL_SIMPLE_BUS=y |
| 14 | CONFIG_DWAPB_GPIO=y |
| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 15 | CONFIG_DM_ETH=y |
| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 16 | CONFIG_ETH_DESIGNWARE=y |