| Bin Meng | db5eec8 | 2015-05-25 22:35:05 +0800 | [diff] [blame] | 1 | Intel Interrupt Router Device Binding |
| 2 | ===================================== |
| 3 | |
| 4 | The device tree node which describes the operation of the Intel Interrupt Router |
| 5 | device is as follows: |
| 6 | |
| 7 | Required properties : |
| 8 | - reg : Specifies the interrupt router's PCI configuration space address as |
| 9 | defined by the Open Firmware spec. |
| 10 | - compatible = "intel,irq-router" |
| 11 | - intel,pirq-config : Specifies the IRQ routing register programming mechanism. |
| 12 | Valid values are: |
| 13 | "pci": IRQ routing is controlled by PCI configuration registers |
| 14 | "ibase": IRQ routing is in the memory-mapped IBASE register block |
| 15 | - intel,ibase-offset : IBASE register offset in the interrupt router's PCI |
| 16 | configuration space, required only if intel,pirq-config = "ibase". |
| Bin Meng | c3b03ea | 2016-05-07 07:46:14 -0700 | [diff] [blame] | 17 | - intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must |
| 18 | be specified. The 8-bit ACTL register is seen on ICH series chipset, like |
| 19 | ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register. |
| 20 | - intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either |
| 21 | in the interrupt router's PCI configuration space, or IBASE. |
| Bin Meng | db5eec8 | 2015-05-25 22:35:05 +0800 | [diff] [blame] | 22 | - intel,pirq-link : Specifies the PIRQ link information with two cells. The |
| 23 | first cell is the register offset that controls the first PIRQ link routing. |
| 24 | The second cell is the total number of PIRQ links the router supports. |
| Bin Meng | d803f54 | 2018-06-12 01:26:46 -0700 | [diff] [blame] | 25 | - intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links, |
| 26 | encoded as 2 cells a group for each link. The first cell is the PIRQ link |
| 27 | number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing |
| 28 | register offset from the interrupt router's base address. If this property |
| 29 | is omitted, it indicates a consecutive register offset from the first PIRQ |
| 30 | link, as specified by the first cell of intel,pirq-link. |
| Simon Glass | 3c5eeb9 | 2015-07-27 15:47:26 -0600 | [diff] [blame] | 31 | - intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the |
| 32 | 8259 PIC. Bit N is 1 means IRQ N is available to be routed. |
| Bin Meng | db5eec8 | 2015-05-25 22:35:05 +0800 | [diff] [blame] | 33 | - intel,pirq-routing : Specifies all PCI devices' IRQ routing information, |
| 34 | encoded as 3 cells a group for a device. The first cell is the device's PCI |
| 35 | bus number, device number and function number encoding with PCI_BDF() macro. |
| 36 | The second cell is the PCI interrupt pin used by this device. The last cell |
| 37 | is which PIRQ line the PCI interrupt pin is routed to. |
| 38 | |
| 39 | |
| 40 | Example |
| 41 | ------- |
| 42 | |
| 43 | #include <dt-bindings/interrupt-router/intel-irq.h> |
| 44 | |
| 45 | irq-router@1f,0 { |
| 46 | reg = <0x0000f800 0 0 0 0>; |
| 47 | compatible = "intel,irq-router"; |
| 48 | intel,pirq-config = "pci"; |
| 49 | intel,pirq-link = <0x60 8>; |
| 50 | intel,pirq-mask = <0xdef8>; |
| 51 | intel,pirq-routing = < |
| 52 | PCI_BDF(0, 2, 0) INTA PIRQA |
| 53 | PCI_BDF(0, 3, 0) INTA PIRQB |
| 54 | PCI_BDF(0, 8, 0) INTA PIRQC |
| 55 | PCI_BDF(0, 8, 1) INTB PIRQD |
| 56 | PCI_BDF(1, 6, 0) INTA PIRQE |
| 57 | PCI_BDF(1, 6, 1) INTB PIRQF |
| 58 | PCI_BDF(1, 6, 2) INTC PIRQG |
| 59 | PCI_BDF(1, 6, 3) INTD PIRQH |
| 60 | >; |
| 61 | }; |