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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Fabio Estevama7b1dc92011-05-13 03:15:11 +00002/*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 *
Fabio Estevam60a7ec22011-09-22 08:07:20 +00005 * Configuration settings for the MX53SMD Freescale board.
Fabio Estevama7b1dc92011-05-13 03:15:11 +00006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Fabio Estevam60a7ec22011-09-22 08:07:20 +000011#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
12
Fabio Estevama7b1dc92011-05-13 03:15:11 +000013#include <asm/arch/imx-regs.h>
14
15#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000016#define CONFIG_SETUP_MEMORY_TAGS
17#define CONFIG_INITRD_TAG
Fabio Estevam5db5f412013-04-24 14:44:26 +000018#define CONFIG_REVISION_TAG
Fabio Estevama7b1dc92011-05-13 03:15:11 +000019
Gong Qianyu52de2e52015-10-26 19:47:42 +080020#define CONFIG_SYS_FSL_CLK
Fabio Estevam0bd0e852014-04-22 15:34:57 -030021
Fabio Estevama7b1dc92011-05-13 03:15:11 +000022/* Size of malloc() pool */
23#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
24
Fabio Estevama7b1dc92011-05-13 03:15:11 +000025#define CONFIG_MXC_UART
Stefano Babic1ca47d92011-11-22 15:22:39 +010026#define CONFIG_MXC_UART_BASE UART1_BASE
Fabio Estevama7b1dc92011-05-13 03:15:11 +000027
28/* I2C Configs */
trem03997412013-09-21 18:13:36 +020029#define CONFIG_SYS_I2C
30#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +020031#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
32#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -070033#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000034
35/* MMC Configs */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000036#define CONFIG_SYS_FSL_ESDHC_ADDR 0
37#define CONFIG_SYS_FSL_ESDHC_NUM 1
38
Fabio Estevama7b1dc92011-05-13 03:15:11 +000039/* Eth Configs */
40#define CONFIG_HAS_ETH1
Fabio Estevama7b1dc92011-05-13 03:15:11 +000041
42#define CONFIG_FEC_MXC
43#define IMX_FEC_BASE FEC_BASE_ADDR
44#define CONFIG_FEC_MXC_PHYADDR 0x1F
45
Fabio Estevama7b1dc92011-05-13 03:15:11 +000046/* allow to overwrite serial and ethaddr */
47#define CONFIG_ENV_OVERWRITE
Fabio Estevama7b1dc92011-05-13 03:15:11 +000048
49/* Command definition */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000050
Wolfgang Grandegger96529e22011-10-17 08:21:56 +000051#define CONFIG_ETHPRIME "FEC0"
Fabio Estevama7b1dc92011-05-13 03:15:11 +000052
53#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000054
55#define CONFIG_EXTRA_ENV_SETTINGS \
56 "script=boot.scr\0" \
57 "uimage=uImage\0" \
58 "mmcdev=0\0" \
59 "mmcpart=2\0" \
60 "mmcroot=/dev/mmcblk0p3 rw\0" \
61 "mmcrootfstype=ext3 rootwait\0" \
62 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
63 "root=${mmcroot} " \
64 "rootfstype=${mmcrootfstype}\0" \
65 "loadbootscript=" \
66 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
67 "bootscript=echo Running bootscript from mmc ...; " \
68 "source\0" \
69 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
70 "mmcboot=echo Booting from mmc ...; " \
71 "run mmcargs; " \
72 "bootm\0" \
73 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
74 "root=/dev/nfs " \
75 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
76 "netboot=echo Booting from net ...; " \
77 "run netargs; " \
78 "dhcp ${uimage}; bootm\0" \
79
80#define CONFIG_BOOTCOMMAND \
Andrew Bradforde1c7c8a2012-10-01 05:06:52 +000081 "mmc dev ${mmcdev}; if mmc rescan; then " \
Fabio Estevama7b1dc92011-05-13 03:15:11 +000082 "if run loadbootscript; then " \
83 "run bootscript; " \
84 "else " \
85 "if run loaduimage; then " \
86 "run mmcboot; " \
87 "else run netboot; " \
88 "fi; " \
89 "fi; " \
90 "else run netboot; fi"
91#define CONFIG_ARP_TIMEOUT 200UL
92
93/* Miscellaneous configurable options */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000094
Fabio Estevama7b1dc92011-05-13 03:15:11 +000095#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
96
Fabio Estevama7b1dc92011-05-13 03:15:11 +000097/* Physical Memory Map */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000098#define PHYS_SDRAM_1 CSD0_BASE_ADDR
99#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
100#define PHYS_SDRAM_2 CSD1_BASE_ADDR
101#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
102#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
103
104#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
105#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
106#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
107
108#define CONFIG_SYS_INIT_SP_OFFSET \
109 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
110#define CONFIG_SYS_INIT_SP_ADDR \
111 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
112
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900113/* environment organization */
Fabio Estevama7b1dc92011-05-13 03:15:11 +0000114#define CONFIG_SYS_MMC_ENV_DEV 0
115
Fabio Estevama7b1dc92011-05-13 03:15:11 +0000116#endif /* __CONFIG_H */