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Heiko Schocherac1956e2006-04-20 08:42:42 +02001/*
2 * Configuation settings for the BuS EB+MCF-EV123 boards.
3 *
4 * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef _CONFIG_EB_MCF_EV123_H_
26#define _CONFIG_EB_MCF_EV123_H_
27
28#define CONFIG_EB_MCF_EV123
29
30#undef DEBUG
31#undef CFG_HALT_BEFOR_RAM_JUMP
32#undef ET_DEBUG
Wolfgang Denkf7290752006-06-10 22:00:40 +020033
Heiko Schocherac1956e2006-04-20 08:42:42 +020034/*
35 * High Level Configuration Options (easy to change)
36 */
37
38#define CONFIG_MCF52x2 /* define processor family */
39#define CONFIG_M5282 /* define processor type */
40
41#define CONFIG_MISC_INIT_R
42
TsiChungLiewceaf3332007-08-15 19:55:10 -050043#define CONFIG_MCFUART
44#define CFG_UART_PORT (0)
Heiko Schocherac1956e2006-04-20 08:42:42 +020045#define CONFIG_BAUDRATE 9600
46#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
47
48#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
49
50#define CONFIG_BOOTCOMMAND "printenv"
51
52/* Configuration for environment
53 * Environment is embedded in u-boot in the second sector of the flash
54 */
55#ifndef CONFIG_MONITOR_IS_IN_RAM
56#define CFG_ENV_ADDR 0xF003C000 /* End of 256K */
57#define CFG_ENV_SECT_SIZE 0x4000
58#define CFG_ENV_IS_IN_FLASH 1
59/*
60#define CFG_ENV_IS_EMBEDDED 1
61#define CFG_ENV_ADDR_REDUND 0xF0018000
62#define CFG_ENV_SECT_SIZE_REDUND 0x4000
63*/
64#else
65#define CFG_ENV_ADDR 0xFFE04000
66#define CFG_ENV_SECT_SIZE 0x2000
67#define CFG_ENV_IS_IN_FLASH 1
68#endif
69
Heiko Schocherac1956e2006-04-20 08:42:42 +020070
Jon Loeligerdbb2b542007-07-07 20:56:05 -050071/*
Jon Loeligerf5709d12007-07-10 09:02:57 -050072 * BOOTP options
73 */
74#define CONFIG_BOOTP_BOOTFILESIZE
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_GATEWAY
77#define CONFIG_BOOTP_HOSTNAME
78
79
80/*
Jon Loeligerdbb2b542007-07-07 20:56:05 -050081 * Command line configuration.
82 */
83#include <config_cmd_default.h>
84
85#undef CONFIG_CMD_LOADB
TsiChungLiewceaf3332007-08-15 19:55:10 -050086#define CONFIG_CMD_MII
87#define CONFIG_CMD_NET
Jon Loeligerdbb2b542007-07-07 20:56:05 -050088
TsiChungLiewceaf3332007-08-15 19:55:10 -050089#define CONFIG_MCFFEC
90#ifdef CONFIG_MCFFEC
91# define CONFIG_NET_MULTI 1
92# define CONFIG_MII 1
93# define CFG_DISCOVER_PHY
94# define CFG_RX_ETH_BUFFER 8
95# define CFG_FAULT_ECHO_LINK_DOWN
96
97# define CFG_FEC0_PINMUX 0
98# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
99# define MCFFEC_TOUT_LOOP 50000
100/* If CFG_DISCOVER_PHY is not defined - hardcoded */
101# ifndef CFG_DISCOVER_PHY
102# define FECDUPLEX FULL
103# define FECSPEED _100BASET
104# else
105# ifndef CFG_FAULT_ECHO_LINK_DOWN
106# define CFG_FAULT_ECHO_LINK_DOWN
107# endif
108# endif /* CFG_DISCOVER_PHY */
109#endif
110
111#ifdef CONFIG_MCFFEC
112# define CONFIG_ETHADDR 00:CF:52:82:EB:01
113# define CONFIG_IPADDR 192.162.1.2
114# define CONFIG_NETMASK 255.255.255.0
115# define CONFIG_SERVERIP 192.162.1.1
116# define CONFIG_GATEWAYIP 192.162.1.1
117# define CONFIG_OVERWRITE_ETHADDR_ONCE
118#endif /* CONFIG_MCFFEC */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200119
120#define CONFIG_BOOTDELAY 5
121#define CFG_PROMPT "\nEV123 U-Boot> "
122#define CFG_LONGHELP /* undef to save memory */
123
Jon Loeligerdbb2b542007-07-07 20:56:05 -0500124#if defined(CONFIG_CMD_KGDB)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200125#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
126#else
127#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
128#endif
129#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
130#define CFG_MAXARGS 16 /* max number of command args */
131#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
132
133#define CFG_LOAD_ADDR 0x20000
134
135#define CFG_MEMTEST_START 0x100000
136#define CFG_MEMTEST_END 0x400000
137/*#define CFG_DRAM_TEST 1 */
138#undef CFG_DRAM_TEST
139
140/* Clock and PLL Configuration */
Wolfgang Denkf7290752006-06-10 22:00:40 +0200141#define CFG_HZ 10000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200142#define CFG_CLK 58982400 /* 9,8304MHz * 6 */
143
144/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
145
Wolfgang Denkf7290752006-06-10 22:00:40 +0200146#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200147#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
148
149/*
150 * Low Level Configuration Settings
151 * (address mappings, register initial values, etc.)
152 * You should know what you are doing if you make changes here.
153 */
154#define CFG_MBAR 0x40000000
155
Heiko Schocherac1956e2006-04-20 08:42:42 +0200156/*-----------------------------------------------------------------------
157 * Definitions for initial stack pointer and data area (in DPRAM)
158 */
159#define CFG_INIT_RAM_ADDR 0x20000000
160#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
161#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
162#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
163#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
164
165/*-----------------------------------------------------------------------
166 * Start addresses for the final memory configuration
167 * (Set up by the startup code)
168 * Please note that CFG_SDRAM_BASE _must_ start at 0
169 */
170#define CFG_SDRAM_BASE1 0x00000000
171#define CFG_SDRAM_SIZE1 16 /* SDRAM size in MB */
172
173/*
174#define CFG_SDRAM_BASE0 CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
175#define CFG_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
176
177#define CFG_SDRAM_BASE CFG_SDRAM_BASE1
178#define CFG_SDRAM_SIZE CFG_SDRAM_SIZE1
179
180#define CFG_FLASH_BASE 0xFFE00000
181#define CFG_INT_FLASH_BASE 0xF0000000
TsiChungLiewceaf3332007-08-15 19:55:10 -0500182#define CFG_INT_FLASH_ENABLE 0x21
Heiko Schocherac1956e2006-04-20 08:42:42 +0200183
184/* If M5282 port is fully implemented the monitor base will be behind
185 * the vector table. */
186#if (TEXT_BASE != CFG_INT_FLASH_BASE)
Wolfgang Denkf7290752006-06-10 22:00:40 +0200187#define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200188#else
189#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
190#endif
191
192#define CFG_MONITOR_LEN 0x20000
193#define CFG_MALLOC_LEN (256 << 10)
194#define CFG_BOOTPARAMS_LEN 64*1024
195
196/*
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization ??
200 */
201#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
202
203/*-----------------------------------------------------------------------
204 * FLASH organization
205 */
206#define CFG_MAX_FLASH_SECT 35
207#define CFG_MAX_FLASH_BANKS 2
208#define CFG_FLASH_ERASE_TOUT 10000000
209#define CFG_FLASH_PROTECTION
210
211/*-----------------------------------------------------------------------
212 * Cache Configuration
213 */
214#define CFG_CACHELINE_SIZE 16
215
216/*-----------------------------------------------------------------------
217 * Memory bank definitions
218 */
219
220#define CFG_CS0_BASE CFG_FLASH_BASE
221#define CFG_CS0_SIZE 2*1024*1024
222#define CFG_CS0_WIDTH 16
223#define CFG_CS0_RO 0
224#define CFG_CS0_WS 6
225
226#define CFG_CS3_BASE 0xE0000000
227#define CFG_CS3_SIZE 1*1024*1024
228#define CFG_CS3_WIDTH 16
229#define CFG_CS3_RO 0
230#define CFG_CS3_WS 6
231
232/*-----------------------------------------------------------------------
233 * Port configuration
234 */
235#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
236#define CFG_PADDR 0x0000000
237#define CFG_PADAT 0x0000000
238
239#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
240#define CFG_PBDDR 0x0000000
241#define CFG_PBDAT 0x0000000
242
243#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
244#define CFG_PCDDR 0x0000000
245#define CFG_PCDAT 0x0000000
246
247#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
248#define CFG_PCDDR 0x0000000
249#define CFG_PCDAT 0x0000000
250
251#define CFG_PEHLPAR 0xC0
252#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
253#define CFG_DDRUA 0x05
254#define CFG_PJPAR 0xFF;
255
256/*-----------------------------------------------------------------------
257 * CCM configuration
258 */
259
260#define CFG_CCM_SIZ 0
261
262/*---------------------------------------------------------------------*/
263#endif /* _CONFIG_M5282EVB_H */
264/*---------------------------------------------------------------------*/