blob: 7013bf97167fa0127130e8383c36b3651a1adbc3 [file] [log] [blame]
Lionel Debieve11985d12025-04-01 15:14:09 +02001// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
4 */
5
6#define LOG_CATEGORY UCLASS_NOP
7
8#include <dm.h>
9#include <asm/io.h>
10#include <dm/device.h>
11#include <dm/device_compat.h>
12#include <dm/lists.h>
13#include <linux/bitfield.h>
14#include <mach/etzpc.h>
15
16/* ETZPC peripheral as firewall bus */
17/* ETZPC registers */
18#define ETZPC_DECPROT 0x10
19#define ETZPC_HWCFGR 0x3F0
20
21/* ETZPC miscellaneous */
22#define ETZPC_PROT_MASK GENMASK(1, 0)
23#define ETZPC_PROT_A7NS 0x3
24#define ETZPC_DECPROT_SHIFT 1
25
26#define IDS_PER_DECPROT_REGS 16
27
28#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8)
29#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16)
30
31/*
32 * struct stm32_etzpc_plat: Information about ETZPC device
33 *
34 * @base: Base address of ETZPC
35 * @max_entries: Number of securable peripherals in ETZPC
36 */
37struct stm32_etzpc_plat {
38 void *base;
39 unsigned int max_entries;
40};
41
42static int etzpc_parse_feature_domain(ofnode node, struct ofnode_phandle_args *args)
43{
44 int ret;
45
46 ret = ofnode_parse_phandle_with_args(node, "access-controllers",
47 "#access-controller-cells", 0,
48 0, args);
49 if (ret) {
50 log_debug("failed to parse access-controller (%d)\n", ret);
51 return ret;
52 }
53
54 if (args->args_count != 1) {
55 log_debug("invalid domain args_count: %d\n", args->args_count);
56 return -EINVAL;
57 }
58
59 return 0;
60}
61
62static int etzpc_check_access(void *base, u32 id)
63{
64 u32 reg_offset, offset, sec_val;
65
66 /* Check access configuration, 16 peripherals per register */
67 reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
68 offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
69
70 /* Verify peripheral is non-secure and attributed to cortex A7 */
71 sec_val = (readl(base + reg_offset) >> offset) & ETZPC_PROT_MASK;
72 if (sec_val != ETZPC_PROT_A7NS) {
73 log_debug("Invalid bus configuration: reg_offset %#x, value %d\n",
74 reg_offset, sec_val);
75 return -EACCES;
76 }
77
78 return 0;
79}
80
81int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id)
82{
83 struct stm32_etzpc_plat *plat;
84 struct ofnode_phandle_args args;
85 struct udevice *dev;
86 int err;
87
88 err = etzpc_parse_feature_domain(device_node, &args);
89 if (err)
90 return err;
91
92 if (id == -1U)
93 id = args.args[0];
94
95 err = uclass_get_device_by_ofnode(UCLASS_NOP, args.node, &dev);
96 if (err || dev->driver != DM_DRIVER_GET(stm32_etzpc)) {
97 log_err("No device found\n");
98 return -EINVAL;
99 }
100
101 plat = dev_get_plat(dev);
102
103 if (id >= plat->max_entries) {
104 dev_err(dev, "Invalid sys bus ID for %s\n", ofnode_get_name(device_node));
105 return -EINVAL;
106 }
107
108 return etzpc_check_access(plat->base, id);
109}
110
111int stm32_etzpc_check_access(ofnode device_node)
112{
113 return stm32_etzpc_check_access_by_id(device_node, -1U);
114}
115
116static int stm32_etzpc_bind(struct udevice *dev)
117{
118 struct stm32_etzpc_plat *plat = dev_get_plat(dev);
119 struct ofnode_phandle_args args;
120 u32 nb_per, nb_master;
121 int ret = 0, err = 0;
122 ofnode node, parent;
123
124 plat->base = dev_read_addr_ptr(dev);
125 if (!plat->base) {
126 dev_err(dev, "can't get registers base address\n");
127 return -ENOENT;
128 }
129
130 /* Get number of etzpc entries*/
131 nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC,
132 readl(plat->base + ETZPC_HWCFGR));
133 nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC,
134 readl(plat->base + ETZPC_HWCFGR));
135 plat->max_entries = nb_per + nb_master;
136
137 parent = dev_ofnode(dev);
138 for (node = ofnode_first_subnode(parent);
139 ofnode_valid(node);
140 node = ofnode_next_subnode(node)) {
141 const char *node_name = ofnode_get_name(node);
142
143 if (!ofnode_is_enabled(node))
144 continue;
145
146 err = etzpc_parse_feature_domain(node, &args);
147 if (err) {
148 dev_err(dev, "%s failed to parse child on bus (%d)\n", node_name, err);
149 continue;
150 }
151
152 if (!ofnode_equal(args.node, parent)) {
153 dev_err(dev, "%s phandle to %s\n",
154 node_name, ofnode_get_name(args.node));
155 continue;
156 }
157
158 if (args.args[0] >= plat->max_entries) {
159 dev_err(dev, "Invalid sys bus ID for %s\n", node_name);
160 return -EINVAL;
161 }
162
163 err = etzpc_check_access(plat->base, args.args[0]);
164 if (err) {
165 dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err);
166 continue;
167 }
168
169 err = lists_bind_fdt(dev, node, NULL, NULL,
170 gd->flags & GD_FLG_RELOC ? false : true);
171 if (err) {
172 ret = err;
173 dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret);
174 }
175 }
176
177 if (ret)
178 dev_err(dev, "Some child failed to bind (%d)\n", ret);
179
180 return ret;
181}
182
183static const struct udevice_id stm32_etzpc_ids[] = {
184 { .compatible = "st,stm32-etzpc" },
185 {},
186};
187
188U_BOOT_DRIVER(stm32_etzpc) = {
189 .name = "stm32_etzpc",
190 .id = UCLASS_NOP,
191 .of_match = stm32_etzpc_ids,
192 .bind = stm32_etzpc_bind,
193 .plat_auto = sizeof(struct stm32_etzpc_plat),
194};