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Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +02001/*
2 * URB OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * usb-ohci.h
8 */
9
Becky Bruce4abaacb2010-06-30 13:05:44 -050010/*
11 * e.g. PCI controllers need this
12 */
13#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
14# define ohci_readl(a) __swap_32(*((volatile u32 *)(a)))
15# define ohci_writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
16#else
17# define ohci_readl(a) (*((volatile u32 *)(a)))
18# define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
19#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
20
Wolfgang Denk2c195722006-06-26 11:06:00 +020021/* functions for doing board or CPU specific setup/cleanup */
Mateusz Zalegad862f892013-10-04 19:22:26 +020022int usb_board_stop(void);
Markus Klotzbuecher98095512006-05-23 10:33:11 +020023
Mateusz Zalegad862f892013-10-04 19:22:26 +020024int usb_cpu_init(void);
25int usb_cpu_stop(void);
26int usb_cpu_init_fail(void);
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +020027
28static int cc_to_error[16] = {
29
30/* mapping of the OHCI CC status to error codes */
31 /* No Error */ 0,
32 /* CRC Error */ USB_ST_CRC_ERR,
33 /* Bit Stuff */ USB_ST_BIT_ERR,
34 /* Data Togg */ USB_ST_CRC_ERR,
35 /* Stall */ USB_ST_STALLED,
36 /* DevNotResp */ -1,
37 /* PIDCheck */ USB_ST_BIT_ERR,
38 /* UnExpPID */ USB_ST_BIT_ERR,
39 /* DataOver */ USB_ST_BUF_ERR,
40 /* DataUnder */ USB_ST_BUF_ERR,
41 /* reservd */ -1,
42 /* reservd */ -1,
43 /* BufferOver */ USB_ST_BUF_ERR,
44 /* BuffUnder */ USB_ST_BUF_ERR,
45 /* Not Access */ -1,
46 /* Not Access */ -1
47};
48
Remy Bohmer172a1132008-09-16 14:55:43 +020049static const char *cc_to_string[16] = {
50 "No Error",
51 "CRC: Last data packet from endpoint contained a CRC error.",
52 "BITSTUFFING: Last data packet from endpoint contained a bit " \
53 "stuffing violation",
54 "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
55 "that did not match the expected value.",
56 "STALL: TD was moved to the Done Queue because the endpoint returned" \
57 " a STALL PID",
58 "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
59 "not provide a handshake (OUT)",
60 "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
61 "(IN) or handshake (OUT)",
62 "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
63 "value is not defined.",
64 "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
65 "either the size of the maximum data packet allowed\n" \
66 "from the endpoint (found in MaximumPacketSize field\n" \
67 "of ED) or the remaining buffer size.",
68 "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
69 "and that amount was not sufficient to fill the\n" \
70 "specified buffer",
71 "reserved1",
72 "reserved2",
73 "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
74 "than it could be written to system memory",
75 "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
76 "system memory fast enough to keep up with data USB " \
77 "data rate.",
78 "NOT ACCESSED: This code is set by software before the TD is placed" \
79 "on a list to be processed by the HC.(1)",
80 "NOT ACCESSED: This code is set by software before the TD is placed" \
81 "on a list to be processed by the HC.(2)",
82};
83
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +020084/* ED States */
85
86#define ED_NEW 0x00
87#define ED_UNLINK 0x01
88#define ED_OPER 0x02
89#define ED_DEL 0x04
90#define ED_URB_DEL 0x08
91
92/* usb_ohci_ed */
93struct ed {
94 __u32 hwINFO;
95 __u32 hwTailP;
96 __u32 hwHeadP;
97 __u32 hwNextED;
98
99 struct ed *ed_prev;
100 __u8 int_period;
101 __u8 int_branch;
102 __u8 int_load;
103 __u8 int_interval;
104 __u8 state;
105 __u8 type;
106 __u16 last_iso;
107 struct ed *ed_rm_list;
108
109 struct usb_device *usb_dev;
Zhang Wei8d15efa2007-06-06 10:08:14 +0200110 void *purb;
111 __u32 unused[2];
Peter Tyser21d2cd22009-04-20 11:08:46 -0500112} __attribute__((aligned(16)));
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200113typedef struct ed ed_t;
114
115
116/* TD info field */
117#define TD_CC 0xf0000000
118#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
119#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
120#define TD_EC 0x0C000000
121#define TD_T 0x03000000
122#define TD_T_DATA0 0x02000000
123#define TD_T_DATA1 0x03000000
124#define TD_T_TOGGLE 0x00000000
125#define TD_R 0x00040000
126#define TD_DI 0x00E00000
127#define TD_DI_SET(X) (((X) & 0x07)<< 21)
128#define TD_DP 0x00180000
129#define TD_DP_SETUP 0x00000000
130#define TD_DP_IN 0x00100000
131#define TD_DP_OUT 0x00080000
132
133#define TD_ISO 0x00010000
134#define TD_DEL 0x00020000
135
136/* CC Codes */
137#define TD_CC_NOERROR 0x00
138#define TD_CC_CRC 0x01
139#define TD_CC_BITSTUFFING 0x02
140#define TD_CC_DATATOGGLEM 0x03
141#define TD_CC_STALL 0x04
142#define TD_DEVNOTRESP 0x05
143#define TD_PIDCHECKFAIL 0x06
144#define TD_UNEXPECTEDPID 0x07
145#define TD_DATAOVERRUN 0x08
146#define TD_DATAUNDERRUN 0x09
147#define TD_BUFFEROVERRUN 0x0C
148#define TD_BUFFERUNDERRUN 0x0D
149#define TD_NOTACCESSED 0x0F
150
151
152#define MAXPSW 1
153
154struct td {
155 __u32 hwINFO;
156 __u32 hwCBP; /* Current Buffer Pointer */
157 __u32 hwNextTD; /* Next TD Pointer */
158 __u32 hwBE; /* Memory Buffer End Pointer */
159
Markus Klotzbuecher661ffe52006-11-27 11:43:09 +0100160/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200161 __u16 hwPSW[MAXPSW];
Markus Klotzbuecher661ffe52006-11-27 11:43:09 +0100162/* #endif */
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200163 __u8 unused;
164 __u8 index;
165 struct ed *ed;
166 struct td *next_dl_td;
167 struct usb_device *usb_dev;
168 int transfer_len;
169 __u32 data;
170
171 __u32 unused2[2];
Peter Tyser21d2cd22009-04-20 11:08:46 -0500172} __attribute__((aligned(32)));
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200173typedef struct td td_t;
174
175#define OHCI_ED_SKIP (1 << 14)
176
177/*
178 * The HCCA (Host Controller Communications Area) is a 256 byte
179 * structure defined in the OHCI spec. that the host controller is
180 * told the base address of. It must be 256-byte aligned.
181 */
182
183#define NUM_INTS 32 /* part of the OHCI standard */
184struct ohci_hcca {
185 __u32 int_table[NUM_INTS]; /* Interrupt ED table */
Markus Klotzbuecher661ffe52006-11-27 11:43:09 +0100186#if defined(CONFIG_MPC5200)
187 __u16 pad1; /* set to 0 on each frame_no change */
188 __u16 frame_no; /* current frame number */
189#else
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200190 __u16 frame_no; /* current frame number */
191 __u16 pad1; /* set to 0 on each frame_no change */
Markus Klotzbuecher661ffe52006-11-27 11:43:09 +0100192#endif
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200193 __u32 done_head; /* info returned for an interrupt */
194 u8 reserved_for_hc[116];
Peter Tyser21d2cd22009-04-20 11:08:46 -0500195} __attribute__((aligned(256)));
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200196
197
198/*
199 * Maximum number of root hub ports.
200 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
202# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
Markus Klotzbuecher661ffe52006-11-27 11:43:09 +0100203#endif
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200204
205/*
206 * This is the structure of the OHCI controller's memory mapped I/O
Becky Bruce4abaacb2010-06-30 13:05:44 -0500207 * region. This is Memory Mapped I/O. You must use the ohci_readl() and
208 * ohci_writel() macros defined in this file to access these!!
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200209 */
210struct ohci_regs {
211 /* control and status registers */
212 __u32 revision;
213 __u32 control;
214 __u32 cmdstatus;
215 __u32 intrstatus;
216 __u32 intrenable;
217 __u32 intrdisable;
218 /* memory pointers */
219 __u32 hcca;
220 __u32 ed_periodcurrent;
221 __u32 ed_controlhead;
222 __u32 ed_controlcurrent;
223 __u32 ed_bulkhead;
224 __u32 ed_bulkcurrent;
225 __u32 donehead;
226 /* frame counters */
227 __u32 fminterval;
228 __u32 fmremaining;
229 __u32 fmnumber;
230 __u32 periodicstart;
231 __u32 lsthresh;
232 /* Root hub ports */
233 struct ohci_roothub_regs {
234 __u32 a;
235 __u32 b;
236 __u32 status;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200237 __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200238 } roothub;
Peter Tyser21d2cd22009-04-20 11:08:46 -0500239} __attribute__((aligned(32)));
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200240
Yuri Tikhonov11af42c2008-09-04 11:19:05 +0200241/* Some EHCI controls */
242#define EHCI_USBCMD_OFF 0x20
243#define EHCI_USBCMD_HCRESET (1 << 1)
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200244
245/* OHCI CONTROL AND STATUS REGISTER MASKS */
246
247/*
248 * HcControl (control) register masks
249 */
250#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
251#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
252#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
253#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
254#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
255#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
256#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
257#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
258#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
259
260/* pre-shifted values for HCFS */
261# define OHCI_USB_RESET (0 << 6)
262# define OHCI_USB_RESUME (1 << 6)
263# define OHCI_USB_OPER (2 << 6)
264# define OHCI_USB_SUSPEND (3 << 6)
265
266/*
267 * HcCommandStatus (cmdstatus) register masks
268 */
269#define OHCI_HCR (1 << 0) /* host controller reset */
270#define OHCI_CLF (1 << 1) /* control list filled */
271#define OHCI_BLF (1 << 2) /* bulk list filled */
272#define OHCI_OCR (1 << 3) /* ownership change request */
273#define OHCI_SOC (3 << 16) /* scheduling overrun count */
274
275/*
276 * masks used with interrupt registers:
277 * HcInterruptStatus (intrstatus)
278 * HcInterruptEnable (intrenable)
279 * HcInterruptDisable (intrdisable)
280 */
281#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
282#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
283#define OHCI_INTR_SF (1 << 2) /* start frame */
284#define OHCI_INTR_RD (1 << 3) /* resume detect */
285#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
286#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
287#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
288#define OHCI_INTR_OC (1 << 30) /* ownership change */
289#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
290
291
292/* Virtual Root HUB */
293struct virt_root_hub {
294 int devnum; /* Address of Root Hub endpoint */
295 void *dev; /* was urb */
296 void *int_addr;
297 int send;
298 int interval;
299};
300
301/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
302
303/* destination of request */
304#define RH_INTERFACE 0x01
305#define RH_ENDPOINT 0x02
306#define RH_OTHER 0x03
307
308#define RH_CLASS 0x20
309#define RH_VENDOR 0x40
310
311/* Requests: bRequest << 8 | bmRequestType */
312#define RH_GET_STATUS 0x0080
313#define RH_CLEAR_FEATURE 0x0100
314#define RH_SET_FEATURE 0x0300
315#define RH_SET_ADDRESS 0x0500
316#define RH_GET_DESCRIPTOR 0x0680
317#define RH_SET_DESCRIPTOR 0x0700
318#define RH_GET_CONFIGURATION 0x0880
319#define RH_SET_CONFIGURATION 0x0900
320#define RH_GET_STATE 0x0280
321#define RH_GET_INTERFACE 0x0A80
322#define RH_SET_INTERFACE 0x0B00
323#define RH_SYNC_FRAME 0x0C80
324/* Our Vendor Specific Request */
325#define RH_SET_EP 0x2000
326
327
328/* Hub port features */
329#define RH_PORT_CONNECTION 0x00
330#define RH_PORT_ENABLE 0x01
331#define RH_PORT_SUSPEND 0x02
332#define RH_PORT_OVER_CURRENT 0x03
333#define RH_PORT_RESET 0x04
334#define RH_PORT_POWER 0x08
335#define RH_PORT_LOW_SPEED 0x09
336
337#define RH_C_PORT_CONNECTION 0x10
338#define RH_C_PORT_ENABLE 0x11
339#define RH_C_PORT_SUSPEND 0x12
340#define RH_C_PORT_OVER_CURRENT 0x13
341#define RH_C_PORT_RESET 0x14
342
343/* Hub features */
344#define RH_C_HUB_LOCAL_POWER 0x00
345#define RH_C_HUB_OVER_CURRENT 0x01
346
347#define RH_DEVICE_REMOTE_WAKEUP 0x00
348#define RH_ENDPOINT_STALL 0x01
349
350#define RH_ACK 0x01
351#define RH_REQ_ERR -1
352#define RH_NACK 0x00
353
354
355/* OHCI ROOT HUB REGISTER MASKS */
356
357/* roothub.portstatus [i] bits */
358#define RH_PS_CCS 0x00000001 /* current connect status */
359#define RH_PS_PES 0x00000002 /* port enable status*/
360#define RH_PS_PSS 0x00000004 /* port suspend status */
361#define RH_PS_POCI 0x00000008 /* port over current indicator */
362#define RH_PS_PRS 0x00000010 /* port reset status */
363#define RH_PS_PPS 0x00000100 /* port power status */
364#define RH_PS_LSDA 0x00000200 /* low speed device attached */
365#define RH_PS_CSC 0x00010000 /* connect status change */
366#define RH_PS_PESC 0x00020000 /* port enable status change */
367#define RH_PS_PSSC 0x00040000 /* port suspend status change */
368#define RH_PS_OCIC 0x00080000 /* over current indicator change */
369#define RH_PS_PRSC 0x00100000 /* port reset status change */
370
371/* roothub.status bits */
372#define RH_HS_LPS 0x00000001 /* local power status */
373#define RH_HS_OCI 0x00000002 /* over current indicator */
374#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
375#define RH_HS_LPSC 0x00010000 /* local power status change */
376#define RH_HS_OCIC 0x00020000 /* over current indicator change */
377#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
378
379/* roothub.b masks */
380#define RH_B_DR 0x0000ffff /* device removable flags */
381#define RH_B_PPCM 0xffff0000 /* port power control mask */
382
383/* roothub.a masks */
384#define RH_A_NDP (0xff << 0) /* number of downstream ports */
385#define RH_A_PSM (1 << 8) /* power switching mode */
386#define RH_A_NPS (1 << 9) /* no power switching */
387#define RH_A_DT (1 << 10) /* device type (mbz) */
388#define RH_A_OCPM (1 << 11) /* over current protection mode */
389#define RH_A_NOCP (1 << 12) /* no over current protection */
390#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
391
392/* urb */
393#define N_URB_TD 48
394typedef struct
395{
396 ed_t *ed;
397 __u16 length; /* number of tds associated with this request */
398 __u16 td_cnt; /* number of tds already serviced */
Zhang Wei8d15efa2007-06-06 10:08:14 +0200399 struct usb_device *dev;
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200400 int state;
401 unsigned long pipe;
Zhang Wei8d15efa2007-06-06 10:08:14 +0200402 void *transfer_buffer;
403 int transfer_buffer_length;
404 int interval;
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200405 int actual_length;
Zhang Wei8d15efa2007-06-06 10:08:14 +0200406 int finished;
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200407 td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
408} urb_priv_t;
409#define URB_DEL 1
410
411/*
412 * This is the full ohci controller description
413 *
414 * Note how the "proper" USB information is just
415 * a subset of what the full implementation needs. (Linus)
416 */
417
418
419typedef struct ohci {
420 struct ohci_hcca *hcca; /* hcca */
421 /*dma_addr_t hcca_dma;*/
422
423 int irq;
424 int disabled; /* e.g. got a UE, we're hung */
425 int sleeping;
426 unsigned long flags; /* for HC bugs */
427
428 struct ohci_regs *regs; /* OHCI controller's memory */
429
Zhang Wei8d15efa2007-06-06 10:08:14 +0200430 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200431 ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
432 ed_t *ed_bulktail; /* last endpoint of bulk list */
433 ed_t *ed_controltail; /* last endpoint of control list */
434 int intrstatus;
435 __u32 hc_control; /* copy of the hc control reg */
436 struct usb_device *dev[32];
437 struct virt_root_hub rh;
438
439 const char *slot_name;
440} ohci_t;
441
442#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
443
444struct ohci_device {
445 ed_t ed[NUM_EDS];
446 int ed_cnt;
447};
448
449/* hcd */
450/* endpoint */
451static int ep_link(ohci_t * ohci, ed_t * ed);
452static int ep_unlink(ohci_t * ohci, ed_t * ed);
Zhang Wei8d15efa2007-06-06 10:08:14 +0200453static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe,
454 int interval, int load);
Markus Klotzbuecherd8d023f2006-05-22 16:33:54 +0200455
456/*-------------------------------------------------------------------------*/
457
458/* we need more TDs than EDs */
459#define NUM_TD 64
460
461/* +1 so we can align the storage */
462td_t gtd[NUM_TD+1];
463/* pointers to aligned storage */
464td_t *ptd;
465
466/* TDs ... */
467static inline struct td *
468td_alloc (struct usb_device *usb_dev)
469{
470 int i;
471 struct td *td;
472
473 td = NULL;
474 for (i = 0; i < NUM_TD; i++)
475 {
476 if (ptd[i].usb_dev == NULL)
477 {
478 td = &ptd[i];
479 td->usb_dev = usb_dev;
480 break;
481 }
482 }
483
484 return td;
485}
486
487static inline void
488ed_free (struct ed *ed)
489{
490 ed->usb_dev = NULL;
491}