blob: f1e64a3438857e16ac875c9f0abe388b18cfa592 [file] [log] [blame]
Bin Mengc85a5be2018-10-15 02:21:23 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 *
5 * VirtIO PCI bus transport driver
6 * Ported from Linux drivers/virtio/virtio_pci*.c
7 */
8
9#include <common.h>
10#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Bin Mengc85a5be2018-10-15 02:21:23 -070012#include <virtio_types.h>
13#include <virtio.h>
14#include <virtio_ring.h>
15#include <dm/device.h>
Simon Glassc06c1be2020-05-10 11:40:08 -060016#include <linux/bug.h>
Bin Mengc85a5be2018-10-15 02:21:23 -070017#include <linux/compat.h>
Simon Glassdbd79542020-05-10 11:40:11 -060018#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070019#include <linux/err.h>
Bin Mengc85a5be2018-10-15 02:21:23 -070020#include <linux/io.h>
21#include "virtio_pci.h"
22
23#define VIRTIO_PCI_DRV_NAME "virtio-pci.m"
24
25/* PCI device ID in the range 0x1040 to 0x107f */
26#define VIRTIO_PCI_VENDOR_ID 0x1af4
27#define VIRTIO_PCI_DEVICE_ID00 0x1040
28#define VIRTIO_PCI_DEVICE_ID01 0x1041
29#define VIRTIO_PCI_DEVICE_ID02 0x1042
30#define VIRTIO_PCI_DEVICE_ID03 0x1043
31#define VIRTIO_PCI_DEVICE_ID04 0x1044
32#define VIRTIO_PCI_DEVICE_ID05 0x1045
33#define VIRTIO_PCI_DEVICE_ID06 0x1046
34#define VIRTIO_PCI_DEVICE_ID07 0x1047
35#define VIRTIO_PCI_DEVICE_ID08 0x1048
36#define VIRTIO_PCI_DEVICE_ID09 0x1049
37#define VIRTIO_PCI_DEVICE_ID0A 0x104a
38#define VIRTIO_PCI_DEVICE_ID0B 0x104b
39#define VIRTIO_PCI_DEVICE_ID0C 0x104c
40#define VIRTIO_PCI_DEVICE_ID0D 0x104d
41#define VIRTIO_PCI_DEVICE_ID0E 0x104e
42#define VIRTIO_PCI_DEVICE_ID0F 0x104f
43#define VIRTIO_PCI_DEVICE_ID10 0x1050
44#define VIRTIO_PCI_DEVICE_ID11 0x1051
45#define VIRTIO_PCI_DEVICE_ID12 0x1052
46#define VIRTIO_PCI_DEVICE_ID13 0x1053
47#define VIRTIO_PCI_DEVICE_ID14 0x1054
48#define VIRTIO_PCI_DEVICE_ID15 0x1055
49#define VIRTIO_PCI_DEVICE_ID16 0x1056
50#define VIRTIO_PCI_DEVICE_ID17 0x1057
51#define VIRTIO_PCI_DEVICE_ID18 0x1058
52#define VIRTIO_PCI_DEVICE_ID19 0x1059
53#define VIRTIO_PCI_DEVICE_ID1A 0x105a
54#define VIRTIO_PCI_DEVICE_ID1B 0x105b
55#define VIRTIO_PCI_DEVICE_ID1C 0x105c
56#define VIRTIO_PCI_DEVICE_ID1D 0x105d
57#define VIRTIO_PCI_DEVICE_ID1E 0x105e
58#define VIRTIO_PCI_DEVICE_ID1F 0x105f
59#define VIRTIO_PCI_DEVICE_ID20 0x1060
60#define VIRTIO_PCI_DEVICE_ID21 0x1061
61#define VIRTIO_PCI_DEVICE_ID22 0x1062
62#define VIRTIO_PCI_DEVICE_ID23 0x1063
63#define VIRTIO_PCI_DEVICE_ID24 0x1064
64#define VIRTIO_PCI_DEVICE_ID25 0x1065
65#define VIRTIO_PCI_DEVICE_ID26 0x1066
66#define VIRTIO_PCI_DEVICE_ID27 0x1067
67#define VIRTIO_PCI_DEVICE_ID28 0x1068
68#define VIRTIO_PCI_DEVICE_ID29 0x1069
69#define VIRTIO_PCI_DEVICE_ID2A 0x106a
70#define VIRTIO_PCI_DEVICE_ID2B 0x106b
71#define VIRTIO_PCI_DEVICE_ID2C 0x106c
72#define VIRTIO_PCI_DEVICE_ID2D 0x106d
73#define VIRTIO_PCI_DEVICE_ID2E 0x106e
74#define VIRTIO_PCI_DEVICE_ID2F 0x106f
75#define VIRTIO_PCI_DEVICE_ID30 0x1070
76#define VIRTIO_PCI_DEVICE_ID31 0x1071
77#define VIRTIO_PCI_DEVICE_ID32 0x1072
78#define VIRTIO_PCI_DEVICE_ID33 0x1073
79#define VIRTIO_PCI_DEVICE_ID34 0x1074
80#define VIRTIO_PCI_DEVICE_ID35 0x1075
81#define VIRTIO_PCI_DEVICE_ID36 0x1076
82#define VIRTIO_PCI_DEVICE_ID37 0x1077
83#define VIRTIO_PCI_DEVICE_ID38 0x1078
84#define VIRTIO_PCI_DEVICE_ID39 0x1079
85#define VIRTIO_PCI_DEVICE_ID3A 0x107a
86#define VIRTIO_PCI_DEVICE_ID3B 0x107b
87#define VIRTIO_PCI_DEVICE_ID3C 0x107c
88#define VIRTIO_PCI_DEVICE_ID3D 0x107d
89#define VIRTIO_PCI_DEVICE_ID3E 0x107e
90#define VIRTIO_PCI_DEVICE_ID3F 0x107f
91
92/**
93 * virtio pci transport driver private data
94 *
95 * @common: pci transport device common register block base
96 * @notify_base: pci transport device notify register block base
Andrew Scull5cda9c02022-04-21 16:11:02 +000097 * @notify_len: pci transport device notify register block length
Bin Mengc85a5be2018-10-15 02:21:23 -070098 * @device: pci transport device device-specific register block base
99 * @device_len: pci transport device device-specific register block length
100 * @notify_offset_multiplier: multiply queue_notify_off by this value
101 */
102struct virtio_pci_priv {
103 struct virtio_pci_common_cfg __iomem *common;
104 void __iomem *notify_base;
Andrew Scull5cda9c02022-04-21 16:11:02 +0000105 u32 notify_len;
Bin Mengc85a5be2018-10-15 02:21:23 -0700106 void __iomem *device;
107 u32 device_len;
108 u32 notify_offset_multiplier;
109};
110
111static int virtio_pci_get_config(struct udevice *udev, unsigned int offset,
112 void *buf, unsigned int len)
113{
114 struct virtio_pci_priv *priv = dev_get_priv(udev);
115 u8 b;
116 __le16 w;
117 __le32 l;
118
Andrew Sculla78d0562022-04-21 16:11:01 +0000119 if (!priv->device)
120 return -ENOSYS;
121
122 if (offset + len > priv->device_len)
123 return -EINVAL;
Bin Mengc85a5be2018-10-15 02:21:23 -0700124
125 switch (len) {
126 case 1:
127 b = ioread8(priv->device + offset);
128 memcpy(buf, &b, sizeof(b));
129 break;
130 case 2:
131 w = cpu_to_le16(ioread16(priv->device + offset));
132 memcpy(buf, &w, sizeof(w));
133 break;
134 case 4:
135 l = cpu_to_le32(ioread32(priv->device + offset));
136 memcpy(buf, &l, sizeof(l));
137 break;
138 case 8:
139 l = cpu_to_le32(ioread32(priv->device + offset));
140 memcpy(buf, &l, sizeof(l));
141 l = cpu_to_le32(ioread32(priv->device + offset + sizeof(l)));
142 memcpy(buf + sizeof(l), &l, sizeof(l));
143 break;
144 default:
Andrew Sculla78d0562022-04-21 16:11:01 +0000145 return -EINVAL;
Bin Mengc85a5be2018-10-15 02:21:23 -0700146 }
147
148 return 0;
149}
150
151static int virtio_pci_set_config(struct udevice *udev, unsigned int offset,
152 const void *buf, unsigned int len)
153{
154 struct virtio_pci_priv *priv = dev_get_priv(udev);
155 u8 b;
156 __le16 w;
157 __le32 l;
158
Andrew Sculla78d0562022-04-21 16:11:01 +0000159 if (!priv->device)
160 return -ENOSYS;
161
162 if (offset + len > priv->device_len)
163 return -EINVAL;
Bin Mengc85a5be2018-10-15 02:21:23 -0700164
165 switch (len) {
166 case 1:
167 memcpy(&b, buf, sizeof(b));
168 iowrite8(b, priv->device + offset);
169 break;
170 case 2:
171 memcpy(&w, buf, sizeof(w));
172 iowrite16(le16_to_cpu(w), priv->device + offset);
173 break;
174 case 4:
175 memcpy(&l, buf, sizeof(l));
176 iowrite32(le32_to_cpu(l), priv->device + offset);
177 break;
178 case 8:
179 memcpy(&l, buf, sizeof(l));
180 iowrite32(le32_to_cpu(l), priv->device + offset);
181 memcpy(&l, buf + sizeof(l), sizeof(l));
182 iowrite32(le32_to_cpu(l), priv->device + offset + sizeof(l));
183 break;
184 default:
Andrew Sculla78d0562022-04-21 16:11:01 +0000185 return -EINVAL;
Bin Mengc85a5be2018-10-15 02:21:23 -0700186 }
187
188 return 0;
189}
190
191static int virtio_pci_generation(struct udevice *udev, u32 *counter)
192{
193 struct virtio_pci_priv *priv = dev_get_priv(udev);
194
195 *counter = ioread8(&priv->common->config_generation);
196
197 return 0;
198}
199
200static int virtio_pci_get_status(struct udevice *udev, u8 *status)
201{
202 struct virtio_pci_priv *priv = dev_get_priv(udev);
203
204 *status = ioread8(&priv->common->device_status);
205
206 return 0;
207}
208
209static int virtio_pci_set_status(struct udevice *udev, u8 status)
210{
211 struct virtio_pci_priv *priv = dev_get_priv(udev);
212
213 /* We should never be setting status to 0 */
214 WARN_ON(status == 0);
215
216 iowrite8(status, &priv->common->device_status);
217
218 return 0;
219}
220
221static int virtio_pci_reset(struct udevice *udev)
222{
223 struct virtio_pci_priv *priv = dev_get_priv(udev);
224
225 /* 0 status means a reset */
226 iowrite8(0, &priv->common->device_status);
227
228 /*
229 * After writing 0 to device_status, the driver MUST wait for a read
230 * of device_status to return 0 before reinitializing the device.
231 * This will flush out the status write, and flush in device writes,
232 * including MSI-X interrupts, if any.
233 */
234 while (ioread8(&priv->common->device_status))
235 udelay(1000);
236
237 return 0;
238}
239
240static int virtio_pci_get_features(struct udevice *udev, u64 *features)
241{
242 struct virtio_pci_priv *priv = dev_get_priv(udev);
243
244 iowrite32(0, &priv->common->device_feature_select);
245 *features = ioread32(&priv->common->device_feature);
246 iowrite32(1, &priv->common->device_feature_select);
247 *features |= ((u64)ioread32(&priv->common->device_feature) << 32);
248
249 return 0;
250}
251
252static int virtio_pci_set_features(struct udevice *udev)
253{
254 struct virtio_pci_priv *priv = dev_get_priv(udev);
255 struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
256
257 if (!__virtio_test_bit(udev, VIRTIO_F_VERSION_1)) {
258 debug("virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1\n");
259 return -EINVAL;
260 }
261
262 iowrite32(0, &priv->common->guest_feature_select);
263 iowrite32((u32)uc_priv->features, &priv->common->guest_feature);
264 iowrite32(1, &priv->common->guest_feature_select);
265 iowrite32(uc_priv->features >> 32, &priv->common->guest_feature);
266
267 return 0;
268}
269
270static struct virtqueue *virtio_pci_setup_vq(struct udevice *udev,
271 unsigned int index)
272{
273 struct virtio_pci_priv *priv = dev_get_priv(udev);
274 struct virtio_pci_common_cfg __iomem *cfg = priv->common;
275 struct virtqueue *vq;
276 u16 num;
277 u64 addr;
278 int err;
279
280 if (index >= ioread16(&cfg->num_queues))
281 return ERR_PTR(-ENOENT);
282
283 /* Select the queue we're interested in */
284 iowrite16(index, &cfg->queue_select);
285
286 /* Check if queue is either not available or already active */
287 num = ioread16(&cfg->queue_size);
288 if (!num || ioread16(&cfg->queue_enable))
289 return ERR_PTR(-ENOENT);
290
291 if (num & (num - 1)) {
292 printf("(%s): bad queue size %u", udev->name, num);
293 return ERR_PTR(-EINVAL);
294 }
295
296 /* Create the vring */
297 vq = vring_create_virtqueue(index, num, VIRTIO_PCI_VRING_ALIGN, udev);
298 if (!vq) {
299 err = -ENOMEM;
300 goto error_available;
301 }
302
303 /* Activate the queue */
304 iowrite16(virtqueue_get_vring_size(vq), &cfg->queue_size);
305
306 addr = virtqueue_get_desc_addr(vq);
307 iowrite32((u32)addr, &cfg->queue_desc_lo);
308 iowrite32(addr >> 32, &cfg->queue_desc_hi);
309
310 addr = virtqueue_get_avail_addr(vq);
311 iowrite32((u32)addr, &cfg->queue_avail_lo);
312 iowrite32(addr >> 32, &cfg->queue_avail_hi);
313
314 addr = virtqueue_get_used_addr(vq);
315 iowrite32((u32)addr, &cfg->queue_used_lo);
316 iowrite32(addr >> 32, &cfg->queue_used_hi);
317
318 iowrite16(1, &cfg->queue_enable);
319
320 return vq;
321
322error_available:
323 return ERR_PTR(err);
324}
325
326static void virtio_pci_del_vq(struct virtqueue *vq)
327{
328 struct virtio_pci_priv *priv = dev_get_priv(vq->vdev);
329 unsigned int index = vq->index;
330
331 iowrite16(index, &priv->common->queue_select);
332
333 /* Select and deactivate the queue */
334 iowrite16(0, &priv->common->queue_enable);
335
336 vring_del_virtqueue(vq);
337}
338
339static int virtio_pci_del_vqs(struct udevice *udev)
340{
341 struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
342 struct virtqueue *vq, *n;
343
344 list_for_each_entry_safe(vq, n, &uc_priv->vqs, list)
345 virtio_pci_del_vq(vq);
346
347 return 0;
348}
349
350static int virtio_pci_find_vqs(struct udevice *udev, unsigned int nvqs,
351 struct virtqueue *vqs[])
352{
353 int i;
354
355 for (i = 0; i < nvqs; ++i) {
356 vqs[i] = virtio_pci_setup_vq(udev, i);
357 if (IS_ERR(vqs[i])) {
358 virtio_pci_del_vqs(udev);
359 return PTR_ERR(vqs[i]);
360 }
361 }
362
363 return 0;
364}
365
366static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq)
367{
368 struct virtio_pci_priv *priv = dev_get_priv(udev);
369 u16 off;
370
371 /* Select the queue we're interested in */
372 iowrite16(vq->index, &priv->common->queue_select);
373
374 /* get offset of notification word for this vq */
375 off = ioread16(&priv->common->queue_notify_off);
376
377 /*
Andrew Scull5cda9c02022-04-21 16:11:02 +0000378 * Check the effective offset is in bounds and leaves space for the
379 * notification, which is just a single 16-bit value since
380 * VIRTIO_F_NOTIFICATION_DATA isn't negotiated by the drivers.
381 */
382 off *= priv->notify_offset_multiplier;
383 if (off > priv->notify_len - sizeof(u16))
384 return -EIO;
385
386 /*
Bin Mengc85a5be2018-10-15 02:21:23 -0700387 * We write the queue's selector into the notification register
388 * to signal the other end
389 */
Andrew Scull5cda9c02022-04-21 16:11:02 +0000390 iowrite16(vq->index, priv->notify_base + off);
Bin Mengc85a5be2018-10-15 02:21:23 -0700391
392 return 0;
393}
394
395/**
396 * virtio_pci_find_capability - walk capabilities to find device info
397 *
398 * @udev: the transport device
399 * @cfg_type: the VIRTIO_PCI_CAP_* value we seek
Andrew Scullf53c0572022-04-21 16:11:04 +0000400 * @cap_size: expected size of the capability
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000401 * @cap: capability read from the config space
Bin Mengc85a5be2018-10-15 02:21:23 -0700402 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100403 * Return: offset of the configuration structure
Bin Mengc85a5be2018-10-15 02:21:23 -0700404 */
Andrew Scullf53c0572022-04-21 16:11:04 +0000405static int virtio_pci_find_capability(struct udevice *udev, u8 cfg_type,
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000406 size_t cap_size,
407 struct virtio_pci_cap *cap)
Bin Mengc85a5be2018-10-15 02:21:23 -0700408{
409 int pos;
410 int offset;
Bin Mengc85a5be2018-10-15 02:21:23 -0700411
Andrew Scullf53c0572022-04-21 16:11:04 +0000412 assert(cap_size >= sizeof(struct virtio_pci_cap));
413 assert(cap_size <= PCI_CFG_SPACE_SIZE);
414
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000415 if (!cap)
416 return 0;
417
Bin Mengc85a5be2018-10-15 02:21:23 -0700418 for (pos = dm_pci_find_capability(udev, PCI_CAP_ID_VNDR);
419 pos > 0;
420 pos = dm_pci_find_next_capability(udev, pos, PCI_CAP_ID_VNDR)) {
Andrew Scullf53c0572022-04-21 16:11:04 +0000421 /* Ensure the capability is within bounds */
422 if (PCI_CFG_SPACE_SIZE - cap_size < pos)
423 return 0;
424
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000425 offset = pos + offsetof(struct virtio_pci_cap, cap_vndr);
426 dm_pci_read_config8(udev, offset, &cap->cap_vndr);
427 offset = pos + offsetof(struct virtio_pci_cap, cap_next);
428 dm_pci_read_config8(udev, offset, &cap->cap_next);
429 offset = pos + offsetof(struct virtio_pci_cap, cap_len);
430 dm_pci_read_config8(udev, offset, &cap->cap_len);
Bin Mengc85a5be2018-10-15 02:21:23 -0700431 offset = pos + offsetof(struct virtio_pci_cap, cfg_type);
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000432 dm_pci_read_config8(udev, offset, &cap->cfg_type);
Bin Mengc85a5be2018-10-15 02:21:23 -0700433 offset = pos + offsetof(struct virtio_pci_cap, bar);
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000434 dm_pci_read_config8(udev, offset, &cap->bar);
435 offset = pos + offsetof(struct virtio_pci_cap, offset);
436 dm_pci_read_config32(udev, offset, &cap->offset);
437 offset = pos + offsetof(struct virtio_pci_cap, length);
438 dm_pci_read_config32(udev, offset, &cap->length);
Bin Mengc85a5be2018-10-15 02:21:23 -0700439
440 /* Ignore structures with reserved BAR values */
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000441 if (cap->bar > 0x5)
Bin Mengc85a5be2018-10-15 02:21:23 -0700442 continue;
443
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000444 if (cap->cfg_type == cfg_type)
Bin Mengc85a5be2018-10-15 02:21:23 -0700445 return pos;
446 }
447
448 return 0;
449}
450
451/**
452 * virtio_pci_map_capability - map base address of the capability
453 *
454 * @udev: the transport device
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000455 * @cap: capability to map
Bin Mengc85a5be2018-10-15 02:21:23 -0700456 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100457 * Return: base address of the capability
Bin Mengc85a5be2018-10-15 02:21:23 -0700458 */
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000459static void __iomem *virtio_pci_map_capability(struct udevice *udev,
460 const struct virtio_pci_cap *cap)
Bin Mengc85a5be2018-10-15 02:21:23 -0700461{
Bin Mengc85a5be2018-10-15 02:21:23 -0700462 ulong base;
463 void __iomem *p;
464
Bin Mengc85a5be2018-10-15 02:21:23 -0700465 /*
466 * TODO: adding 64-bit BAR support
467 *
468 * Per spec, the BAR is permitted to be either 32-bit or 64-bit.
469 * For simplicity, only read the BAR address as 32-bit.
470 */
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000471 base = dm_pci_read_bar32(udev, cap->bar);
472 p = (void __iomem *)base + cap->offset;
Bin Mengc85a5be2018-10-15 02:21:23 -0700473
474 return p;
475}
476
477static int virtio_pci_bind(struct udevice *udev)
478{
479 static int num_devs;
480 char name[20];
481
482 /* Create a unique device name */
483 sprintf(name, "%s#%u", VIRTIO_PCI_DRV_NAME, num_devs++);
484 device_set_name(udev, name);
485
486 return 0;
487}
488
489static int virtio_pci_probe(struct udevice *udev)
490{
Simon Glassb75b15b2020-12-03 16:55:23 -0700491 struct pci_child_plat *pplat = dev_get_parent_plat(udev);
Bin Mengc85a5be2018-10-15 02:21:23 -0700492 struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
493 struct virtio_pci_priv *priv = dev_get_priv(udev);
494 u16 subvendor;
495 u8 revision;
496 int common, notify, device;
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000497 struct virtio_pci_cap common_cap, notify_cap, device_cap;
Bin Mengc85a5be2018-10-15 02:21:23 -0700498 int offset;
499
500 /* We only own devices >= 0x1040 and <= 0x107f: leave the rest. */
501 if (pplat->device < 0x1040 || pplat->device > 0x107f)
502 return -ENODEV;
503
504 /* Transitional devices must not have a PCI revision ID of 0 */
505 dm_pci_read_config8(udev, PCI_REVISION_ID, &revision);
506
507 /* Modern devices: simply use PCI device id, but start from 0x1040. */
508 uc_priv->device = pplat->device - 0x1040;
509 dm_pci_read_config16(udev, PCI_SUBSYSTEM_VENDOR_ID, &subvendor);
510 uc_priv->vendor = subvendor;
511
512 /* Check for a common config: if not, use legacy mode (bar 0) */
Andrew Scullf53c0572022-04-21 16:11:04 +0000513 common = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_COMMON_CFG,
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000514 sizeof(struct virtio_pci_cap),
515 &common_cap);
Bin Mengc85a5be2018-10-15 02:21:23 -0700516 if (!common) {
517 printf("(%s): leaving for legacy driver\n", udev->name);
518 return -ENODEV;
519 }
520
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000521 if (common_cap.length < sizeof(struct virtio_pci_common_cfg)) {
Andrew Scull53d6e1d2022-04-21 16:11:03 +0000522 printf("(%s): virtio common config too small\n", udev->name);
523 return -EINVAL;
524 }
525
Bin Mengc85a5be2018-10-15 02:21:23 -0700526 /* If common is there, notify should be too */
Andrew Scullf53c0572022-04-21 16:11:04 +0000527 notify = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_NOTIFY_CFG,
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000528 sizeof(struct virtio_pci_notify_cap),
529 &notify_cap);
Bin Mengc85a5be2018-10-15 02:21:23 -0700530 if (!notify) {
531 printf("(%s): missing capabilities %i/%i\n", udev->name,
532 common, notify);
533 return -EINVAL;
534 }
535
Andrew Scull3d41dd42022-04-21 16:11:14 +0000536 /* Map configuration structures */
537 priv->common = virtio_pci_map_capability(udev, &common_cap);
538 if (!priv->common) {
539 printf("(%s): could not map common config\n", udev->name);
540 return -EINVAL;
541 }
542
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000543 priv->notify_len = notify_cap.length;
Andrew Scull3d41dd42022-04-21 16:11:14 +0000544 priv->notify_base = virtio_pci_map_capability(udev, &notify_cap);
545 if (!priv->notify_base) {
546 printf("(%s): could not map notify config\n", udev->name);
547 return -EINVAL;
548 }
Andrew Scull5cda9c02022-04-21 16:11:02 +0000549
Bin Mengc85a5be2018-10-15 02:21:23 -0700550 /*
551 * Device capability is only mandatory for devices that have
552 * device-specific configuration.
553 */
Andrew Scullf53c0572022-04-21 16:11:04 +0000554 device = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_DEVICE_CFG,
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000555 sizeof(struct virtio_pci_cap),
556 &device_cap);
Bin Mengc85a5be2018-10-15 02:21:23 -0700557 if (device) {
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000558 priv->device_len = device_cap.length;
559 priv->device = virtio_pci_map_capability(udev, &device_cap);
Andrew Scull3d41dd42022-04-21 16:11:14 +0000560 if (!priv->device) {
561 printf("(%s): could not map device config\n",
562 udev->name);
563 return -EINVAL;
564 }
Bin Mengc85a5be2018-10-15 02:21:23 -0700565 }
566
Bin Mengc85a5be2018-10-15 02:21:23 -0700567 debug("(%p): common @ %p, notify base @ %p, device @ %p\n",
568 udev, priv->common, priv->notify_base, priv->device);
569
570 /* Read notify_off_multiplier from config space */
571 offset = notify + offsetof(struct virtio_pci_notify_cap,
572 notify_off_multiplier);
573 dm_pci_read_config32(udev, offset, &priv->notify_offset_multiplier);
574
575 debug("(%s): device (%d) vendor (%08x) version (%d)\n", udev->name,
576 uc_priv->device, uc_priv->vendor, revision);
577
578 return 0;
579}
580
581static const struct dm_virtio_ops virtio_pci_ops = {
582 .get_config = virtio_pci_get_config,
583 .set_config = virtio_pci_set_config,
584 .generation = virtio_pci_generation,
585 .get_status = virtio_pci_get_status,
586 .set_status = virtio_pci_set_status,
587 .reset = virtio_pci_reset,
588 .get_features = virtio_pci_get_features,
589 .set_features = virtio_pci_set_features,
590 .find_vqs = virtio_pci_find_vqs,
591 .del_vqs = virtio_pci_del_vqs,
592 .notify = virtio_pci_notify,
593};
594
595U_BOOT_DRIVER(virtio_pci_modern) = {
596 .name = VIRTIO_PCI_DRV_NAME,
597 .id = UCLASS_VIRTIO,
598 .ops = &virtio_pci_ops,
599 .bind = virtio_pci_bind,
600 .probe = virtio_pci_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700601 .priv_auto = sizeof(struct virtio_pci_priv),
Bin Mengc85a5be2018-10-15 02:21:23 -0700602};
603
604static struct pci_device_id virtio_pci_supported[] = {
605 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID00) },
606 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID01) },
607 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID02) },
608 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID03) },
609 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID04) },
610 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID05) },
611 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID06) },
612 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID07) },
613 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID08) },
614 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID09) },
615 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0A) },
616 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0B) },
617 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0C) },
618 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0D) },
619 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0E) },
620 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0F) },
621 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID10) },
622 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID11) },
623 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID12) },
624 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID13) },
625 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID14) },
626 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID15) },
627 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID16) },
628 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID17) },
629 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID18) },
630 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID19) },
631 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1A) },
632 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1B) },
633 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1C) },
634 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1D) },
635 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1E) },
636 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1F) },
637 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID20) },
638 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID21) },
639 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID22) },
640 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID23) },
641 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID24) },
642 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID25) },
643 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID26) },
644 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID27) },
645 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID28) },
646 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID29) },
647 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2A) },
648 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2B) },
649 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2C) },
650 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2D) },
651 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2E) },
652 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2F) },
653 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID30) },
654 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID31) },
655 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID32) },
656 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID33) },
657 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID34) },
658 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID35) },
659 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID36) },
660 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID37) },
661 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID38) },
662 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID39) },
663 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3A) },
664 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3B) },
665 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3C) },
666 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3D) },
667 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3E) },
668 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3F) },
669 {},
670};
671
672U_BOOT_PCI_DEVICE(virtio_pci_modern, virtio_pci_supported);