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git01.mediatek.com / filogic / uboot / a61057f7cb8fdb17e2e399708ed54dae98c95118 / . / board / nvidia / seaboard / seaboard.c
blob: 829751112f1c05a586e6c20951d537d86b88eb7b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]2/*
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/io.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -0600[diff] [blame]9#include <asm/mach-types.h>
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]10#include <asm/arch/tegra.h>
Jeroen Hofstee93dfae72014-10-08 22:57:46 +0200[diff] [blame]11#include <asm/arch-tegra/board.h>
Simon Glassea160b12012-01-11 12:42:28 +0000[diff] [blame]12#include <asm/arch/clock.h>
13#include <asm/arch/funcmux.h>
Stephen Warren63315d92012-10-22 06:19:36 +0000[diff] [blame]14#include <asm/arch/gpio.h>
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]15#include <asm/arch/pinmux.h>
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]16#include <asm/gpio.h>
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]17
Simon Glass704e60d2011-11-05 04:46:51 +0000[diff] [blame]18/* TODO: Remove this code when the SPI switch is working */
Tom Rinieb6aadc2021-08-30 09:16:32 -0400[diff] [blame]19#ifndef CONFIG_TARGET_VENTANA
Stephen Warren63315d92012-10-22 06:19:36 +0000[diff] [blame]20void gpio_early_init_uart(void)
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]21{
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]22 /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
Stephen Warren7f20bb22016-05-12 12:07:39 -0600[diff] [blame]23 gpio_request(TEGRA_GPIO(I, 3), "uart_en");
24 gpio_direction_output(TEGRA_GPIO(I, 3), 0);
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]25}
Simon Glass704e60d2011-11-05 04:46:51 +0000[diff] [blame]26#endif
Stephen Warrenffac82e2011-10-31 06:51:37 +0000[diff] [blame]27
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900[diff] [blame]28#ifdef CONFIG_MMC_SDHCI_TEGRA
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]29/*
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]30 * Routine: pin_mux_mmc
31 * Description: setup the pin muxes/tristate values for the SDMMC(s)
32 */
Tom Warren9745cf82013-02-21 12:31:30 +0000[diff] [blame]33void pin_mux_mmc(void)
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]34{
Simon Glassea160b12012-01-11 12:42:28 +0000[diff] [blame]35 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
36 funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]37
38 /* For power GPIO PI6 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]39 pinmux_tristate_disable(PMUX_PINGRP_ATA);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]40 /* For CD GPIO PI5 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]41 pinmux_tristate_disable(PMUX_PINGRP_ATC);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]42}
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]43#endif
Simon Glass5d73a8d2012-02-27 10:52:50 +0000[diff] [blame]44
45void pin_mux_usb(void)
46{
Stephen Warrenf0231872016-09-15 12:19:39 -0600[diff] [blame]47 /* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]48 pinmux_tristate_disable(PMUX_PINGRP_SLXK);
Stephen Warrenf0231872016-09-15 12:19:39 -0600[diff] [blame]49 /* For USB1's ULPI signals */
50 funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
51 pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
52 pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
53 /* USB1 PHY reset GPIO */
54 pinmux_tristate_disable(PMUX_PINGRP_UAC);
Simon Glass5d73a8d2012-02-27 10:52:50 +0000[diff] [blame]55}