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git01.mediatek.com / filogic / uboot / a5b4bdbda8ccd90e08ff2f5b643b50a27d45178e / . / arch / arm / dts / omap3-u-boot.dtsi
blob: 7366ff56932e7760a00fd84f2baf3f2e0e7112f7 [file] [log] [blame]
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap5-u-boot.dtsi"
8 */
9
10/{
11 ocp@68000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]13
14 bandgap@48002524 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]15 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]16 };
17 };
18};
19
20&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]22 reg-shift = <2>;
23};
24
25&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]27 reg-shift = <2>;
28};
29
30&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]32 reg-shift = <2>;
33};
34
35&mmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]37};
38
39&mmc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]41};
42
43&l4_core {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]45};
46
47&scm {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]49};
50
51&scm_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]53};
54
55&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]57};
58
59&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]61};
62
63&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]65};
66
67&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]69};
70
71&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]73};
74
75&gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]77};
78
79&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Anthoine Bourgeois5876d0c2022-06-02 22:27:07 +0200[diff] [blame]81 clock-frequency = <100000>;
Adam Fordb92bc4f2019-02-16 13:31:23 -0600[diff] [blame]82};