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git01.mediatek.com / filogic / uboot / a5b4bdbda8ccd90e08ff2f5b643b50a27d45178e / . / arch / arm / dts / imx8mm-verdin-wifi-dev-u-boot.dtsi
blob: 494229e4e62a020f0b00a0bc7207fe9ac374f2cd [file] [log] [blame]
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2020-2022 Toradex
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
15
16 wdt-reboot {
17 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]19 wdt = <&wdog1>;
20 };
21};
22
23&{/aliases} {
24 eeprom0 = &eeprom_module;
25 eeprom1 = &eeprom_carrier_board;
26 eeprom2 = &eeprom_display_adapter;
27};
28
29&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]31};
32
33&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]35};
36
37&binman_uboot {
38 offset = <0x5fc00>;
39};
40
41&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]43};
44
45&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]47};
48
49&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]51};
52
53&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]55};
56
57&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]59};
60
61&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]63
64 eeprom_module: eeprom@50 {
65 compatible = "i2c-eeprom";
66 pagesize = <16>;
67 reg = <0x50>;
68 };
69};
70
71&i2c2 {
72 status = "okay";
73};
74
75&i2c4 {
76 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
77 eeprom_display_adapter: eeprom@50 {
78 compatible = "i2c-eeprom";
79 pagesize = <16>;
80 reg = <0x50>;
81 };
82
83 /* EEPROM on carrier board */
84 eeprom_carrier_board: eeprom@57 {
85 compatible = "i2c-eeprom";
86 pagesize = <16>;
87 reg = <0x57>;
88 };
89};
90
91&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]93};
94
95&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]97};
98
99&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]101};
102
103&pinctrl_usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]105};
106
107&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]109};
110
111&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]113};
114
115&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]117};
118
119&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]121};
122
123&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]125};
126
127&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]129};
130
131&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]133};