blob: f4ebcbb318b41860727d4cb7d743eefc8f4119e4 [file] [log] [blame]
Michal Simeke116c542018-03-28 15:36:36 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
Michal Simek821e32a2021-05-31 09:50:01 +02005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
Michal Simeke116c542018-03-28 15:36:36 +02006 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
Michal Simekf7b922a2021-05-10 13:14:02 +020015#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
Michal Simeke116c542018-03-28 15:36:36 +020016#include <dt-bindings/phy/phy.h>
17
18/ {
19 model = "ZynqMP ZCU104 RevC";
20 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem3;
Michal Simeke116c542018-03-28 15:36:36 +020024 i2c0 = &i2c1;
25 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +020026 nvmem0 = &eeprom;
Michal Simeke116c542018-03-28 15:36:36 +020027 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &dcc;
31 spi0 = &qspi;
32 usb0 = &usb0;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
38 };
39
40 memory@0 {
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
43 };
Michal Simek9d66a4c2019-08-26 09:40:23 +020044
45 ina226 {
46 compatible = "iio-hwmon";
47 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
48 };
Michal Simek958c0e92020-11-26 14:25:02 +010049
50 clock_8t49n287_5: clk125 {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <125000000>;
54 };
55
56 clock_8t49n287_2: clk26 {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <26000000>;
60 };
61
62 clock_8t49n287_3: clk27 {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <27000000>;
66 };
Michal Simeke116c542018-03-28 15:36:36 +020067};
68
69&can1 {
70 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +020071 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_can1_default>;
Michal Simeke116c542018-03-28 15:36:36 +020073};
74
75&dcc {
76 status = "okay";
77};
78
Michal Simekf390a212019-03-07 08:15:52 +010079&fpd_dma_chan1 {
80 status = "okay";
81};
82
83&fpd_dma_chan2 {
84 status = "okay";
85};
86
87&fpd_dma_chan3 {
88 status = "okay";
89};
90
91&fpd_dma_chan4 {
92 status = "okay";
93};
94
95&fpd_dma_chan5 {
96 status = "okay";
97};
98
99&fpd_dma_chan6 {
100 status = "okay";
101};
102
103&fpd_dma_chan7 {
104 status = "okay";
105};
106
107&fpd_dma_chan8 {
108 status = "okay";
109};
110
Michal Simeke116c542018-03-28 15:36:36 +0200111&gem3 {
112 status = "okay";
113 phy-handle = <&phy0>;
114 phy-mode = "rgmii-id";
Michal Simekf7b922a2021-05-10 13:14:02 +0200115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_gem3_default>;
Michal Simek393decf2019-08-08 12:44:22 +0200117 phy0: ethernet-phy@c {
Michal Simeke116c542018-03-28 15:36:36 +0200118 reg = <0xc>;
119 ti,rx-internal-delay = <0x8>;
120 ti,tx-internal-delay = <0xa>;
121 ti,fifo-depth = <0x1>;
Harini Katakam991a1612019-02-13 17:02:21 +0530122 ti,dp83867-rxctrl-strap-quirk;
Michal Simeke116c542018-03-28 15:36:36 +0200123 };
124};
125
126&gpio {
127 status = "okay";
128};
129
130&gpu {
131 status = "okay";
132};
133
134&i2c1 {
135 status = "okay";
136 clock-frequency = <400000>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200137 pinctrl-names = "default", "gpio";
138 pinctrl-0 = <&pinctrl_i2c1_default>;
139 pinctrl-1 = <&pinctrl_i2c1_gpio>;
140 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
141 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
Michal Simeke116c542018-03-28 15:36:36 +0200142
Michal Simekbea57132018-05-29 15:28:43 +0200143 tca6416_u97: gpio@20 {
Michal Simeke116c542018-03-28 15:36:36 +0200144 compatible = "ti,tca6416";
Michal Simekbea57132018-05-29 15:28:43 +0200145 reg = <0x20>;
Michal Simeke116c542018-03-28 15:36:36 +0200146 gpio-controller;
147 #gpio-cells = <2>;
148 /*
149 * IRQ not connected
150 * Lines:
151 * 0 - IRPS5401_ALERT_B
152 * 1 - HDMI_8T49N241_INT_ALM
153 * 2 - MAX6643_OT_B
154 * 3 - MAX6643_FANFAIL_B
155 * 5 - IIC_MUX_RESET_B
156 * 6 - GEM3_EXP_RESET_B
157 * 7 - FMC_LPC_PRSNT_M2C_B
158 * 4, 10 - 17 - not connected
159 */
160 };
161
162 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
163 i2c-mux@74 { /* u34 */
164 compatible = "nxp,pca9548";
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <0x74>;
168 i2c@0 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 reg = <0>;
172 /*
173 * IIC_EEPROM 1kB memory which uses 256B blocks
174 * where every block has different address.
175 * 0 - 256B address 0x54
176 * 256B - 512B address 0x55
177 * 512B - 768B address 0x56
178 * 768B - 1024B address 0x57
179 */
180 eeprom: eeprom@54 { /* u23 */
181 compatible = "atmel,24c08";
182 reg = <0x54>;
183 #address-cells = <1>;
184 #size-cells = <1>;
185 };
186 };
187
188 i2c@1 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 reg = <1>;
Michal Simek2add7442021-06-03 11:58:08 +0200192 /* 8T49N287 - u182 */
Michal Simeke116c542018-03-28 15:36:36 +0200193 };
194
195 i2c@2 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <2>;
Michal Simek3514e4e2020-03-30 11:35:38 +0200199 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
Michal Simeke116c542018-03-28 15:36:36 +0200200 compatible = "infineon,irps5401";
Michal Simek3514e4e2020-03-30 11:35:38 +0200201 reg = <0x43>; /* pmbus / i2c 0x13 */
Michal Simeke116c542018-03-28 15:36:36 +0200202 };
Michal Simek3514e4e2020-03-30 11:35:38 +0200203 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
Michal Simeke116c542018-03-28 15:36:36 +0200204 compatible = "infineon,irps5401";
Michal Simek3514e4e2020-03-30 11:35:38 +0200205 reg = <0x44>; /* pmbus / i2c 0x14 */
Michal Simeke116c542018-03-28 15:36:36 +0200206 };
207 };
208
Michal Simekee29db12018-05-29 14:45:13 +0200209 i2c@3 {
Michal Simeke116c542018-03-28 15:36:36 +0200210 #address-cells = <1>;
211 #size-cells = <0>;
Michal Simekee29db12018-05-29 14:45:13 +0200212 reg = <3>;
Michal Simek9d66a4c2019-08-26 09:40:23 +0200213 u183: ina226@40 { /* u183 */
Michal Simekee29db12018-05-29 14:45:13 +0200214 compatible = "ti,ina226";
Michal Simek9d66a4c2019-08-26 09:40:23 +0200215 #io-channel-cells = <1>;
Michal Simekee29db12018-05-29 14:45:13 +0200216 reg = <0x40>;
217 shunt-resistor = <5000>;
218 };
Michal Simeke116c542018-03-28 15:36:36 +0200219 };
220
221 i2c@5 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <5>;
225 };
226
227 i2c@7 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 reg = <7>;
231 };
232
Michal Simekee29db12018-05-29 14:45:13 +0200233 /* 4, 6 not connected */
Michal Simeke116c542018-03-28 15:36:36 +0200234 };
235};
236
Michal Simekf7b922a2021-05-10 13:14:02 +0200237&pinctrl0 {
238 status = "okay";
239
240 pinctrl_can1_default: can1-default {
241 mux {
242 function = "can1";
243 groups = "can1_6_grp";
244 };
245
246 conf {
247 groups = "can1_6_grp";
248 slew-rate = <SLEW_RATE_SLOW>;
249 power-source = <IO_STANDARD_LVCMOS18>;
250 drive-strength = <12>;
251 };
252
253 conf-rx {
254 pins = "MIO25";
255 bias-high-impedance;
256 };
257
258 conf-tx {
259 pins = "MIO24";
260 bias-disable;
261 };
262 };
263
264 pinctrl_i2c1_default: i2c1-default {
265 mux {
266 groups = "i2c1_4_grp";
267 function = "i2c1";
268 };
269
270 conf {
271 groups = "i2c1_4_grp";
272 bias-pull-up;
273 slew-rate = <SLEW_RATE_SLOW>;
274 power-source = <IO_STANDARD_LVCMOS18>;
275 drive-strength = <12>;
276 };
277 };
278
279 pinctrl_i2c1_gpio: i2c1-gpio {
280 mux {
281 groups = "gpio0_16_grp", "gpio0_17_grp";
282 function = "gpio0";
283 };
284
285 conf {
286 groups = "gpio0_16_grp", "gpio0_17_grp";
287 slew-rate = <SLEW_RATE_SLOW>;
288 power-source = <IO_STANDARD_LVCMOS18>;
289 drive-strength = <12>;
290 };
291 };
292
293 pinctrl_gem3_default: gem3-default {
294 mux {
295 function = "ethernet3";
296 groups = "ethernet3_0_grp";
297 };
298
299 conf {
300 groups = "ethernet3_0_grp";
301 slew-rate = <SLEW_RATE_SLOW>;
302 power-source = <IO_STANDARD_LVCMOS18>;
303 drive-strength = <12>;
304 };
305
306 conf-rx {
307 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
308 "MIO75";
309 bias-high-impedance;
310 low-power-disable;
311 };
312
313 conf-tx {
314 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
315 "MIO69";
316 bias-disable;
317 low-power-enable;
318 };
319
320 mux-mdio {
321 function = "mdio3";
322 groups = "mdio3_0_grp";
323 };
324
325 conf-mdio {
326 groups = "mdio3_0_grp";
327 slew-rate = <SLEW_RATE_SLOW>;
328 power-source = <IO_STANDARD_LVCMOS18>;
329 bias-disable;
330 };
331 };
332
333 pinctrl_sdhci1_default: sdhci1-default {
334 mux {
335 groups = "sdio1_0_grp";
336 function = "sdio1";
337 };
338
339 conf {
340 groups = "sdio1_0_grp";
341 slew-rate = <SLEW_RATE_SLOW>;
342 power-source = <IO_STANDARD_LVCMOS18>;
343 bias-disable;
344 drive-strength = <12>;
345 };
346
347 mux-cd {
348 groups = "sdio1_cd_0_grp";
349 function = "sdio1_cd";
350 };
351
352 conf-cd {
353 groups = "sdio1_cd_0_grp";
354 bias-high-impedance;
355 bias-pull-up;
356 slew-rate = <SLEW_RATE_SLOW>;
357 power-source = <IO_STANDARD_LVCMOS18>;
358 };
359 };
360
361 pinctrl_uart0_default: uart0-default {
362 mux {
363 groups = "uart0_4_grp";
364 function = "uart0";
365 };
366
367 conf {
368 groups = "uart0_4_grp";
369 slew-rate = <SLEW_RATE_SLOW>;
370 power-source = <IO_STANDARD_LVCMOS18>;
371 drive-strength = <12>;
372 };
373
374 conf-rx {
375 pins = "MIO18";
376 bias-high-impedance;
377 };
378
379 conf-tx {
380 pins = "MIO19";
381 bias-disable;
382 };
383 };
384
385 pinctrl_uart1_default: uart1-default {
386 mux {
387 groups = "uart1_5_grp";
388 function = "uart1";
389 };
390
391 conf {
392 groups = "uart1_5_grp";
393 slew-rate = <SLEW_RATE_SLOW>;
394 power-source = <IO_STANDARD_LVCMOS18>;
395 drive-strength = <12>;
396 };
397
398 conf-rx {
399 pins = "MIO21";
400 bias-high-impedance;
401 };
402
403 conf-tx {
404 pins = "MIO20";
405 bias-disable;
406 };
407 };
408
409 pinctrl_usb0_default: usb0-default {
410 mux {
411 groups = "usb0_0_grp";
412 function = "usb0";
413 };
414
415 conf {
416 groups = "usb0_0_grp";
417 slew-rate = <SLEW_RATE_SLOW>;
418 power-source = <IO_STANDARD_LVCMOS18>;
419 drive-strength = <12>;
420 };
421
422 conf-rx {
423 pins = "MIO52", "MIO53", "MIO55";
424 bias-high-impedance;
425 };
426
427 conf-tx {
428 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
429 "MIO60", "MIO61", "MIO62", "MIO63";
430 bias-disable;
431 };
432 };
433};
434
Michal Simekae7230c2021-06-03 15:18:04 +0200435&psgtr {
436 status = "okay";
437 /* nc, sata, usb3, dp */
438 clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
439 clock-names = "ref1", "ref2", "ref3";
440};
441
Michal Simeke116c542018-03-28 15:36:36 +0200442&qspi {
443 status = "okay";
444 flash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000445 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
Michal Simeke116c542018-03-28 15:36:36 +0200446 #address-cells = <1>;
447 #size-cells = <1>;
448 reg = <0x0>;
449 spi-tx-bus-width = <1>;
450 spi-rx-bus-width = <4>;
451 spi-max-frequency = <108000000>; /* Based on DC1 spec */
Michal Simek70fafdf2020-02-14 14:19:56 +0100452 partition@0 { /* for testing purpose */
Michal Simeke116c542018-03-28 15:36:36 +0200453 label = "qspi-fsbl-uboot";
454 reg = <0x0 0x100000>;
455 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100456 partition@100000 { /* for testing purpose */
Michal Simeke116c542018-03-28 15:36:36 +0200457 label = "qspi-linux";
458 reg = <0x100000 0x500000>;
459 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100460 partition@600000 { /* for testing purpose */
Michal Simeke116c542018-03-28 15:36:36 +0200461 label = "qspi-device-tree";
462 reg = <0x600000 0x20000>;
463 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100464 partition@620000 { /* for testing purpose */
Michal Simeke116c542018-03-28 15:36:36 +0200465 label = "qspi-rootfs";
466 reg = <0x620000 0x5E0000>;
467 };
468 };
469};
470
471&rtc {
472 status = "okay";
Michal Simek958c0e92020-11-26 14:25:02 +0100473};
474
Michal Simeke116c542018-03-28 15:36:36 +0200475&sata {
476 status = "okay";
477 /* SATA OOB timing settings */
478 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
479 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
480 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
481 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
482 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
483 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
484 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
485 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
486 phy-names = "sata-phy";
Michal Simek958c0e92020-11-26 14:25:02 +0100487 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
Michal Simeke116c542018-03-28 15:36:36 +0200488};
489
490/* SD1 with level shifter */
491&sdhci1 {
492 status = "okay";
493 no-1-8-v;
Michal Simekf7b922a2021-05-10 13:14:02 +0200494 pinctrl-names = "default";
495 pinctrl-0 = <&pinctrl_sdhci1_default>;
Michal Simek3b662642020-07-22 17:42:43 +0200496 xlnx,mio-bank = <1>;
Michal Simeke116c542018-03-28 15:36:36 +0200497 disable-wp;
498};
499
Michal Simeke116c542018-03-28 15:36:36 +0200500&uart0 {
501 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_uart0_default>;
Michal Simeke116c542018-03-28 15:36:36 +0200504};
505
506&uart1 {
507 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_uart1_default>;
Michal Simeke116c542018-03-28 15:36:36 +0200510};
511
512/* ULPI SMSC USB3320 */
513&usb0 {
514 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_usb0_default>;
Michal Simeke116c542018-03-28 15:36:36 +0200517};
518
519&dwc3_0 {
520 status = "okay";
521 dr_mode = "host";
522 snps,usb3_lpm_capable;
Michal Simekfe8cb0c2021-05-10 14:55:34 +0200523 phy-names = "usb3-phy";
524 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
Michal Simeke116c542018-03-28 15:36:36 +0200525 maximum-speed = "super-speed";
526};
527
528&watchdog0 {
529 status = "okay";
530};
531
532&xilinx_ams {
533 status = "okay";
534};
535
536&ams_ps {
537 status = "okay";
538};
539
540&ams_pl {
541 status = "okay";
Michal Simek958c0e92020-11-26 14:25:02 +0100542};
543
544&zynqmp_dpdma {
545 status = "okay";
546};
547
548&zynqmp_dpsub {
549 status = "okay";
550 phy-names = "dp-phy0", "dp-phy1";
551 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
552 <&psgtr 0 PHY_TYPE_DP 1 3>;
Michal Simeke116c542018-03-28 15:36:36 +0200553};