| Vasily Khoruzhick | da2f45a | 2019-11-09 11:24:50 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <syscon.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch-rockchip/clock.h> |
| 11 | #include <asm/arch-rockchip/grf_rk3399.h> |
| 12 | #include <asm/arch-rockchip/hardware.h> |
| 13 | #include <asm/arch-rockchip/misc.h> |
| 14 | |
| 15 | #define GRF_IO_VSEL_BT565_SHIFT 0 |
| 16 | #define PMUGRF_CON0_VSEL_SHIFT 8 |
| 17 | |
| 18 | #ifdef CONFIG_MISC_INIT_R |
| 19 | static void setup_iodomain(void) |
| 20 | { |
| 21 | struct rk3399_grf_regs *grf = |
| 22 | syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
| 23 | struct rk3399_pmugrf_regs *pmugrf = |
| 24 | syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
| 25 | |
| 26 | /* BT565 is in 1.8v domain */ |
| 27 | rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); |
| 28 | |
| 29 | /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ |
| 30 | rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); |
| 31 | } |
| 32 | |
| 33 | int misc_init_r(void) |
| 34 | { |
| 35 | const u32 cpuid_offset = 0x7; |
| 36 | const u32 cpuid_length = 0x10; |
| 37 | u8 cpuid[cpuid_length]; |
| 38 | int ret; |
| 39 | |
| 40 | setup_iodomain(); |
| 41 | |
| 42 | ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); |
| 43 | if (ret) |
| 44 | return ret; |
| 45 | |
| 46 | ret = rockchip_cpuid_set(cpuid, cpuid_length); |
| 47 | if (ret) |
| 48 | return ret; |
| 49 | |
| 50 | ret = rockchip_setup_macaddr(); |
| 51 | |
| 52 | return ret; |
| 53 | } |
| 54 | |
| 55 | #endif |