Giulio Benetti | d1203ca | 2020-02-18 20:02:55 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) 2020 |
| 4 | * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> |
| 5 | */ |
| 6 | |
| 7 | / { |
| 8 | chosen { |
| 9 | u-boot,dm-spl; |
| 10 | }; |
Giulio Benetti | f05daef | 2021-05-16 23:57:01 +0200 | [diff] [blame] | 11 | |
| 12 | clocks { |
| 13 | u-boot,dm-spl; |
| 14 | }; |
| 15 | |
| 16 | soc { |
| 17 | u-boot,dm-spl; |
| 18 | }; |
| 19 | }; |
| 20 | |
| 21 | &osc { |
| 22 | u-boot,dm-spl; |
| 23 | }; |
| 24 | |
Jesse Taube | 214f443 | 2022-03-17 14:33:18 -0400 | [diff] [blame] | 25 | &anatop { |
| 26 | u-boot,dm-spl; |
| 27 | }; |
| 28 | |
Giulio Benetti | f05daef | 2021-05-16 23:57:01 +0200 | [diff] [blame] | 29 | &clks { |
| 30 | u-boot,dm-spl; |
| 31 | }; |
| 32 | |
| 33 | &gpio1 { |
| 34 | u-boot,dm-spl; |
Giulio Benetti | d1203ca | 2020-02-18 20:02:55 +0100 | [diff] [blame] | 35 | }; |
| 36 | |
Giulio Benetti | f05daef | 2021-05-16 23:57:01 +0200 | [diff] [blame] | 37 | &gpio2 { |
| 38 | u-boot,dm-spl; |
| 39 | }; |
| 40 | |
| 41 | &gpio3 { |
| 42 | u-boot,dm-spl; |
| 43 | }; |
| 44 | |
| 45 | &gpio5 { |
| 46 | u-boot,dm-spl; |
| 47 | }; |
| 48 | |
Giulio Benetti | d2475f9 | 2021-05-13 12:18:36 +0200 | [diff] [blame] | 49 | &gpt1 { |
| 50 | u-boot,dm-spl; |
| 51 | }; |
| 52 | |
Giulio Benetti | d1203ca | 2020-02-18 20:02:55 +0100 | [diff] [blame] | 53 | &lpuart1 { /* console */ |
| 54 | u-boot,dm-spl; |
| 55 | }; |
| 56 | |
| 57 | &semc { |
Giulio Benetti | f05daef | 2021-05-16 23:57:01 +0200 | [diff] [blame] | 58 | u-boot,dm-spl; |
| 59 | |
Giulio Benetti | d1203ca | 2020-02-18 20:02:55 +0100 | [diff] [blame] | 60 | bank1: bank@0 { |
| 61 | u-boot,dm-spl; |
| 62 | }; |
| 63 | }; |
| 64 | |
| 65 | &iomuxc { |
| 66 | u-boot,dm-spl; |
| 67 | |
| 68 | imxrt1020-evk { |
| 69 | u-boot,dm-spl; |
| 70 | pinctrl_lpuart1: lpuart1grp { |
| 71 | u-boot,dm-spl; |
| 72 | }; |
| 73 | |
| 74 | pinctrl_semc: semcgrp { |
| 75 | u-boot,dm-spl; |
| 76 | }; |
| 77 | |
| 78 | pinctrl_usdhc0: usdhc0grp { |
| 79 | u-boot,dm-spl; |
| 80 | }; |
| 81 | }; |
| 82 | }; |
| 83 | |
| 84 | &usdhc1 { |
| 85 | u-boot,dm-spl; |
| 86 | }; |