arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2022 Logic PD, Inc DBA Beacon EmbeddedWorks
 */

#include "imx8mp-u-boot.dtsi"

/ {
	/* U-Boot does not yet have a proper PCIe clk driver */
	pcie0_refclk: clock-pcie {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&wdog1>;
		bootph-pre-ram;
	};
};

&pcie_phy {
	clocks = <&pcie0_refclk>;
};

&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
	bootph-pre-ram;
};

&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
	bootph-pre-ram;
};

&eqos {
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	/delete-property/ assigned-clock-rates;
};

&ethphy0 {
	reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	reset-assert-us = <15000>;
	reset-deassert-us = <100000>;
};

&fec {
	phy-reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <15>;
	phy-reset-post-delay = <100>;
};

&flexspi {
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};

&gpio1 {
	bootph-pre-ram;
};

&gpio2 {
	bootph-pre-ram;
};

&gpio3 {
	bootph-pre-ram;
};

&gpio4 {
	bootph-pre-ram;
};

&gpio5 {
	bootph-pre-ram;
};

&i2c1 {
	bootph-pre-ram;
};

&i2c2 {
	bootph-pre-ram;
};

&i2c3 {
	bootph-pre-ram;
};

&pca6416 {
	compatible = "ti,tca6416";
	label = "exp4";
};

&pca6416_1 {
	compatible = "ti,tca6416";
	label = "exp4";
};

&pca6416_3 {
	compatible = "ti,tca6416";
	label = "exp2";
};

&pinctrl_i2c1 {
	bootph-pre-ram;
};

&pinctrl_pmic {
	bootph-pre-ram;
};

&pinctrl_reg_usdhc2_vmmc {
	bootph-pre-ram;
};

&pinctrl_uart2 {
	bootph-pre-ram;
};

&pinctrl_usdhc2_gpio {
	bootph-pre-ram;
};

&pinctrl_usdhc2 {
	bootph-pre-ram;
};

&pinctrl_usdhc3 {
	bootph-pre-ram;
};

&pinctrl_wdog {
	bootph-pre-ram;
};

&reg_usdhc2_vmmc {
	bootph-pre-ram;
	u-boot,off-on-delay-us = <20000>;
};

&tpm {
	compatible = "tcg,tpm_tis-spi";
};

&uart2 {
	bootph-pre-ram;
};

&usdhc1 {
	bootph-pre-ram;
	assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};

&usdhc2 {
	bootph-pre-ram;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	assigned-clock-rates = <400000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};

&usdhc3 {
	bootph-pre-ram;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};

&usb3_0 {
	dma-ranges = <0x40000000 0x40000000 0xc0000000>;
};

&usb3_1 {
	dma-ranges = <0x40000000 0x40000000 0xc0000000>;
};

&usb_dwc3_0 {
	compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
	assigned-clock-rates = <400000000>;
};

&usb_dwc3_1 {
	compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
	assigned-clock-rates = <400000000>;
};

&usdhc1 {
	status = "disabled";
};

&wdog1 {
	bootph-pre-ram;
};