blob: 7df8cc516a1ba0be5dc2cbbcbf3a49aed34d1b08 [file] [log] [blame]
Bin Meng9e816df2014-12-17 15:50:48 +08001#
2# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4#
5# SPDX-License-Identifier: GPL-2.0+
6#
7
8U-Boot on x86
9=============
10
11This document describes the information about U-Boot running on x86 targets,
12including supported boards, build instructions, todo list, etc.
13
14Status
15------
16U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17(Chromebook Pixel) has been tested, but it should work with minimal adjustments
18on other x86 boards since coreboot deals with most of the low-level details.
19
20U-Boot also supports booting directly from x86 reset vector without coreboot,
21aka raw support or bare support. Currently Link and Intel Crown Bay board
22support running U-Boot 'bare metal'.
23
24As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
25kernel as part of a FIT image. It also supports a compressed zImage.
26
27Build Instructions
28------------------
29Building U-Boot as a coreboot payload is just like building U-Boot for targets
30on other architectures, like below:
31
32$ make coreboot-x86_defconfig
33$ make all
34
Bin Meng6c6ec432015-01-06 22:14:24 +080035Note this default configuration will build a U-Boot payload for the Link board.
36To build a coreboot payload against another board, you can change the build
37configuration during the 'make menuconfig' process.
38
39x86 architecture --->
40 ...
41 (chromebook_link) Board configuration file
42 (chromebook_link) Board Device Tree Source (dts) file
43 (0x19200000) Board specific Cache-As-RAM (CAR) address
44 (0x4000) Board specific Cache-As-RAM (CAR) size
45
46Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
47to point to a new board. You can also change the Cache-As-RAM (CAR) related
48settings here if the default values do not fit your new board.
49
Bin Meng9e816df2014-12-17 15:50:48 +080050Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
51little bit tricky, as generally it requires several binary blobs which are not
52shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
53not turned on by default in the U-Boot source tree. Firstly, you need turn it
54on by uncommenting the following line in the main U-Boot Makefile:
55
56# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
57
58Link-specific instructions:
59
60First, you need the following binary blobs:
61
62* descriptor.bin - Intel flash descriptor
63* me.bin - Intel Management Engine
64* mrc.bin - Memory Reference Code, which sets up SDRAM
65* video ROM - sets up the display
66
67You can get these binary blobs by:
68
69$ git clone http://review.coreboot.org/p/blobs.git
70$ cd blobs
71
72Find the following files:
73
74* ./mainboard/google/link/descriptor.bin
75* ./mainboard/google/link/me.bin
76* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
77
78The 3rd one should be renamed to mrc.bin.
79As for the video ROM, you can get it here [2].
80Make sure all these binary blobs are put in the board directory.
81
82Now you can build U-Boot and obtain u-boot.rom:
83
84$ make chromebook_link_defconfig
85$ make all
86
87Intel Crown Bay specific instructions:
88
89U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
90Firmware Support Package [4] to perform all the necessary initialization steps
91as documented in the BIOS Writer Guide, including initialization of the CPU,
92memory controller, chipset and certain bus interfaces.
93
94Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
95install it on your host and locate the FSP binary blob. Note this platform
96also requires a Chipset Micro Code (CMC) state machine binary to be present in
97the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
98in this FSP package too.
99
100* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
101* ./Microcode/C0_22211.BIN
102
103Rename the first one to fsp.bin and second one to cmc.bin and put them in the
104board directory.
105
Bin Meng6c6ec432015-01-06 22:14:24 +0800106Now you can build U-Boot and obtain u-boot.rom
Bin Meng9e816df2014-12-17 15:50:48 +0800107
108$ make crownbay_defconfig
109$ make all
110
Bin Meng6c6ec432015-01-06 22:14:24 +0800111Test with coreboot
112------------------
113For testing U-Boot as the coreboot payload, there are things that need be paid
114attention to. coreboot supports loading an ELF executable and a 32-bit plain
115binary, as well as other supported payloads. With the default configuration,
116U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
117generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
118provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
119this capability yet. The command is as follows:
120
121# in the coreboot root directory
122$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
123 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
124
125Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
126symbol address of _start (in arch/x86/cpu/start.S).
127
128If you want to use ELF as the coreboot payload, change U-Boot configuration to
129use CONFIG_OF_EMBED.
130
Bin Meng9e816df2014-12-17 15:50:48 +0800131CPU Microcode
132-------------
133Modern CPU usually requires a special bit stream called microcode [5] to be
134loaded on the processor after power up in order to function properly. U-Boot
135has already integrated these as hex dumps in the source tree.
136
137Driver Model
138------------
139x86 has been converted to use driver model for serial and GPIO.
140
141Device Tree
142-----------
143x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
Bin Meng6c6ec432015-01-06 22:14:24 +0800144be turned on. Not every device on the board is configured via device tree, but
Bin Meng9e816df2014-12-17 15:50:48 +0800145more and more devices will be added as time goes by. Check out the directory
146arch/x86/dts/ for these device tree source files.
147
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700148Useful Commands
149---------------
150
151In keeping with the U-Boot philosophy of providing functions to check and
152adjust internal settings, there are several x86-specific commands that may be
153useful:
154
155hob - Display information about Firmware Support Package (FSP) Hand-off
156 Block. This is only available on platforms which use FSP, mostly
157 Atom.
158iod - Display I/O memory
159iow - Write I/O memory
160mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
161 tell the CPU whether memory is cacheable and if so the cache write
162 mode to use. U-Boot sets up some reasonable values but you can
163 adjust then with this command.
164
Bin Meng9e816df2014-12-17 15:50:48 +0800165TODO List
166---------
Bin Meng9e816df2014-12-17 15:50:48 +0800167- Audio
168- Chrome OS verified boot
169- SMI and ACPI support, to provide platform info and facilities to Linux
170
171References
172----------
173[1] http://www.coreboot.org
174[2] http://www.coreboot.org/~stepan/pci8086,0166.rom
175[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
176[4] http://www.intel.com/fsp
177[5] http://en.wikipedia.org/wiki/Microcode