blob: 461ff6e860a396f0191ae9d536db205b1393e917 [file] [log] [blame]
Marek Vasutffdd4662013-04-28 09:20:03 +00001/*
2 * Freescale i.MX23/i.MX28 LCDIF driver
3 *
4 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21#include <common.h>
22#include <malloc.h>
23#include <video_fb.h>
24
25#include <asm/arch/imx-regs.h>
26#include <asm/arch/clock.h>
27#include <asm/arch/sys_proto.h>
28#include <asm/errno.h>
29#include <asm/io.h>
30
31#include "videomodes.h"
32
33#define PS2KHZ(ps) (1000000000UL / (ps))
34
35static GraphicDevice panel;
36
37/*
38 * DENX M28EVK:
39 * setenv videomode
40 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
41 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
42 */
43
44static void mxs_lcd_init(GraphicDevice *panel,
45 struct ctfb_res_modes *mode, int bpp)
46{
47 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
48 uint32_t word_len = 0, bus_width = 0;
49 uint8_t valid_data = 0;
50
51 /* Kick in the LCDIF clock */
52 mxs_set_lcdclk(PS2KHZ(mode->pixclock));
53
54 /* Restart the LCDIF block */
55 mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
56
57 switch (bpp) {
58 case 24:
59 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
60 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
61 valid_data = 0x7;
62 break;
63 case 18:
64 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
65 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
66 valid_data = 0x7;
67 break;
68 case 16:
69 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
70 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
71 valid_data = 0xf;
72 break;
73 case 8:
74 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
75 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
76 valid_data = 0xf;
77 break;
78 }
79
80 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
81 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
82 &regs->hw_lcdif_ctrl);
83
84 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
85 &regs->hw_lcdif_ctrl1);
86 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
87 &regs->hw_lcdif_transfer_count);
88
89 writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
90 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
91 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
92 mode->vsync_len, &regs->hw_lcdif_vdctrl0);
93 writel(mode->upper_margin + mode->lower_margin +
94 mode->vsync_len + mode->yres,
95 &regs->hw_lcdif_vdctrl1);
96 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
97 (mode->left_margin + mode->right_margin +
98 mode->hsync_len + mode->xres),
99 &regs->hw_lcdif_vdctrl2);
100 writel(((mode->left_margin + mode->hsync_len) <<
101 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
102 (mode->upper_margin + mode->vsync_len),
103 &regs->hw_lcdif_vdctrl3);
104 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
105 &regs->hw_lcdif_vdctrl4);
106
107 writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
108 writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
109
110 /* Flush FIFO first */
111 writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
112
113 /* Sync signals ON */
114 setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
115
116 /* FIFO cleared */
117 writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
118
119 /* RUN! */
120 writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
121}
122
123void *video_hw_init(void)
124{
125 int bpp = -1;
126 char *penv;
127 void *fb;
128 struct ctfb_res_modes mode;
129
130 puts("Video: ");
131
132 /* Suck display configuration from "videomode" variable */
133 penv = getenv("videomode");
134 if (!penv) {
135 printf("MXSFB: 'videomode' variable not set!");
136 return NULL;
137 }
138
139 bpp = video_get_params(&mode, penv);
140
141 /* fill in Graphic device struct */
142 sprintf(panel.modeIdent, "%dx%dx%d",
143 mode.xres, mode.yres, bpp);
144
145 panel.winSizeX = mode.xres;
146 panel.winSizeY = mode.yres;
147 panel.plnSizeX = mode.xres;
148 panel.plnSizeY = mode.yres;
149
150 switch (bpp) {
151 case 24:
152 case 18:
153 panel.gdfBytesPP = 4;
154 panel.gdfIndex = GDF_32BIT_X888RGB;
155 break;
156 case 16:
157 panel.gdfBytesPP = 2;
158 panel.gdfIndex = GDF_16BIT_565RGB;
159 break;
160 case 8:
161 panel.gdfBytesPP = 1;
162 panel.gdfIndex = GDF__8BIT_INDEX;
163 break;
164 default:
165 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
166 return NULL;
167 }
168
169 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
170
171 /* Allocate framebuffer */
172 fb = malloc(panel.memSize);
173 if (!fb) {
174 printf("MXSFB: Error allocating framebuffer!\n");
175 return NULL;
176 }
177
178 /* Wipe framebuffer */
179 memset(fb, 0, panel.memSize);
180
181 panel.frameAdrs = (u32)fb;
182
183 printf("%s\n", panel.modeIdent);
184
185 /* Start framebuffer */
186 mxs_lcd_init(&panel, &mode, bpp);
187
188 return (void *)&panel;
189}