Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 1 | /* |
| 2 | * board/renesas/gose/gose.c |
| 3 | * |
| 4 | * Copyright (C) 2014 Renesas Electronics Corporation |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0 |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <malloc.h> |
| 11 | #include <asm/processor.h> |
| 12 | #include <asm/mach-types.h> |
| 13 | #include <asm/io.h> |
| 14 | #include <asm/errno.h> |
| 15 | #include <asm/arch/sys_proto.h> |
| 16 | #include <asm/gpio.h> |
| 17 | #include <asm/arch/rmobile.h> |
Nobuhiro Iwamatsu | ade3c94 | 2014-12-02 16:52:19 +0900 | [diff] [blame] | 18 | #include <asm/arch/rcar-mstp.h> |
Nobuhiro Iwamatsu | eef1f23 | 2014-11-06 15:42:24 +0900 | [diff] [blame] | 19 | #include <netdev.h> |
| 20 | #include <miiphy.h> |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 21 | #include <i2c.h> |
| 22 | #include "qos.h" |
| 23 | |
| 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
| 26 | #define CLK2MHZ(clk) (clk / 1000 / 1000) |
| 27 | void s_init(void) |
| 28 | { |
| 29 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
| 30 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
| 31 | u32 stc; |
| 32 | |
| 33 | /* Watchdog init */ |
| 34 | writel(0xA5A5A500, &rwdt->rwtcsra); |
| 35 | writel(0xA5A5A500, &swdt->swtcsra); |
| 36 | |
| 37 | /* CPU frequency setting. Set to 1.5GHz */ |
| 38 | stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; |
| 39 | clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); |
| 40 | |
| 41 | /* QoS */ |
| 42 | qos_init(); |
| 43 | } |
| 44 | |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 45 | #define TMU0_MSTP125 (1 << 25) |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 46 | #define SCIF0_MSTP721 (1 << 21) |
Nobuhiro Iwamatsu | eef1f23 | 2014-11-06 15:42:24 +0900 | [diff] [blame] | 47 | #define ETHER_MSTP813 (1 << 13) |
| 48 | |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 49 | int board_early_init_f(void) |
| 50 | { |
| 51 | /* TMU0 */ |
| 52 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
| 53 | |
| 54 | /* SCIF0 */ |
| 55 | mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); |
| 56 | |
Nobuhiro Iwamatsu | eef1f23 | 2014-11-06 15:42:24 +0900 | [diff] [blame] | 57 | /* ETHER */ |
| 58 | mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); |
| 59 | |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 60 | return 0; |
| 61 | } |
| 62 | |
Nobuhiro Iwamatsu | eef1f23 | 2014-11-06 15:42:24 +0900 | [diff] [blame] | 63 | #define PUPR5 0xE6060114 |
| 64 | #define PUPR5_ETH 0x3FFC0000 |
| 65 | #define PUPR5_ETH_MAGIC (1 << 27) |
| 66 | |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 67 | int board_init(void) |
| 68 | { |
| 69 | /* adress of boot parameters */ |
Nobuhiro Iwamatsu | 66fc458 | 2014-11-10 13:58:50 +0900 | [diff] [blame] | 70 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 71 | |
| 72 | /* Init PFC controller */ |
| 73 | r8a7793_pinmux_init(); |
| 74 | |
Nobuhiro Iwamatsu | eef1f23 | 2014-11-06 15:42:24 +0900 | [diff] [blame] | 75 | /* ETHER Enable */ |
| 76 | gpio_request(GPIO_FN_ETH_CRS_DV, NULL); |
| 77 | gpio_request(GPIO_FN_ETH_RX_ER, NULL); |
| 78 | gpio_request(GPIO_FN_ETH_RXD0, NULL); |
| 79 | gpio_request(GPIO_FN_ETH_RXD1, NULL); |
| 80 | gpio_request(GPIO_FN_ETH_LINK, NULL); |
| 81 | gpio_request(GPIO_FN_ETH_REFCLK, NULL); |
| 82 | gpio_request(GPIO_FN_ETH_MDIO, NULL); |
| 83 | gpio_request(GPIO_FN_ETH_TXD1, NULL); |
| 84 | gpio_request(GPIO_FN_ETH_TX_EN, NULL); |
| 85 | gpio_request(GPIO_FN_ETH_TXD0, NULL); |
| 86 | gpio_request(GPIO_FN_ETH_MDC, NULL); |
| 87 | gpio_request(GPIO_FN_IRQ0, NULL); |
| 88 | |
| 89 | mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); |
| 90 | gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ |
| 91 | mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); |
| 92 | |
| 93 | gpio_direction_output(GPIO_GP_5_22, 0); |
| 94 | mdelay(20); |
| 95 | gpio_set_value(GPIO_GP_5_22, 1); |
| 96 | udelay(1); |
| 97 | |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 98 | return 0; |
| 99 | } |
| 100 | |
Nobuhiro Iwamatsu | eef1f23 | 2014-11-06 15:42:24 +0900 | [diff] [blame] | 101 | #define CXR24 0xEE7003C0 /* MAC address high register */ |
| 102 | #define CXR25 0xEE7003C8 /* MAC address low register */ |
| 103 | |
| 104 | int board_eth_init(bd_t *bis) |
| 105 | { |
| 106 | int ret = -ENODEV; |
| 107 | u32 val; |
| 108 | unsigned char enetaddr[6]; |
| 109 | |
| 110 | #ifdef CONFIG_SH_ETHER |
| 111 | ret = sh_eth_initialize(bis); |
| 112 | if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
| 113 | return ret; |
| 114 | |
| 115 | /* Set Mac address */ |
| 116 | val = enetaddr[0] << 24 | enetaddr[1] << 16 | |
| 117 | enetaddr[2] << 8 | enetaddr[3]; |
| 118 | writel(val, CXR24); |
| 119 | |
| 120 | val = enetaddr[4] << 8 | enetaddr[5]; |
| 121 | writel(val, CXR25); |
| 122 | #endif |
| 123 | |
| 124 | return ret; |
| 125 | } |
| 126 | |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 127 | int dram_init(void) |
| 128 | { |
| 129 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
| 130 | |
| 131 | return 0; |
| 132 | } |
| 133 | |
| 134 | const struct rmobile_sysinfo sysinfo = { |
| 135 | CONFIG_RMOBILE_BOARD_STRING |
| 136 | }; |
| 137 | |
Nobuhiro Iwamatsu | 7e40563 | 2014-11-06 15:39:28 +0900 | [diff] [blame] | 138 | void reset_cpu(ulong addr) |
| 139 | { |
| 140 | u8 val; |
| 141 | |
| 142 | i2c_set_bus_num(2); /* PowerIC connected to ch2 */ |
| 143 | i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); |
| 144 | val |= 0x02; |
| 145 | i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); |
| 146 | } |