wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 1 | /*-----------------------------------------------------------------------------+ |
Josh Boyer | 471573b | 2009-08-07 13:53:20 -0400 | [diff] [blame] | 2 | | This source code is dual-licensed. You may use it under the terms of the |
| 3 | | GNU General Public License version 2, or under the license below. |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 4 | | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 5 | | This source code has been made available to you by IBM on an AS-IS |
| 6 | | basis. Anyone receiving this source is licensed under IBM |
| 7 | | copyrights to use it in any way he or she deems fit, including |
| 8 | | copying it, modifying it, compiling it, and redistributing it either |
| 9 | | with or without modifications. No license under IBM patents or |
| 10 | | patent applications is to be implied by the copyright license. |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 11 | | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 12 | | Any user of this software should understand that IBM cannot provide |
| 13 | | technical support for this software and will not be responsible for |
| 14 | | any consequences resulting from the use of this software. |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 15 | | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 16 | | Any person who transfers this source code or any derivative work |
| 17 | | must include the IBM copyright notice, this paragraph, and the |
| 18 | | preceding two paragraphs in the transferred software. |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 19 | | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 20 | | COPYRIGHT I B M CORPORATION 1995 |
| 21 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 22 | +-----------------------------------------------------------------------------*/ |
| 23 | /*-----------------------------------------------------------------------------+ |
| 24 | | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 25 | | File Name: miiphy.c |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 26 | | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 27 | | Function: This module has utilities for accessing the MII PHY through |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 28 | | the EMAC3 macro. |
| 29 | | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 30 | | Author: Mark Wisner |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 31 | | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 32 | +-----------------------------------------------------------------------------*/ |
| 33 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 34 | /* define DEBUG for debugging output (obviously ;-)) */ |
| 35 | #if 0 |
| 36 | #define DEBUG |
| 37 | #endif |
| 38 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 39 | #include <common.h> |
| 40 | #include <asm/processor.h> |
Stefan Roese | 69710095 | 2007-10-23 14:03:17 +0200 | [diff] [blame] | 41 | #include <asm/io.h> |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 42 | #include <ppc_asm.tmpl> |
| 43 | #include <commproc.h> |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 44 | #include <asm/ppc4xx-emac.h> |
| 45 | #include <asm/ppc4xx-mal.h> |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 46 | #include <miiphy.h> |
| 47 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 48 | #if !defined(CONFIG_PHY_CLK_FREQ) |
| 49 | #define CONFIG_PHY_CLK_FREQ 0 |
| 50 | #endif |
| 51 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 52 | /***********************************************************/ |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 53 | /* Dump out to the screen PHY regs */ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 54 | /***********************************************************/ |
| 55 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 56 | void miiphy_dump (char *devname, unsigned char addr) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 57 | { |
| 58 | unsigned long i; |
| 59 | unsigned short data; |
| 60 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 61 | for (i = 0; i < 0x1A; i++) { |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 62 | if (miiphy_read (devname, addr, i, &data)) { |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 63 | printf ("read error for reg %lx\n", i); |
| 64 | return; |
| 65 | } |
| 66 | printf ("Phy reg %lx ==> %4x\n", i, data); |
| 67 | |
| 68 | /* jump to the next set of regs */ |
| 69 | if (i == 0x07) |
| 70 | i = 0x0f; |
| 71 | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 72 | } /* end for loop */ |
| 73 | } /* end dump */ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 74 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 75 | /***********************************************************/ |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 76 | /* (Re)start autonegotiation */ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 77 | /***********************************************************/ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 78 | int phy_setup_aneg (char *devname, unsigned char addr) |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 79 | { |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 80 | u16 bmcr; |
| 81 | |
| 82 | #if defined(CONFIG_PHY_DYNAMIC_ANEG) |
| 83 | /* |
| 84 | * Set up advertisement based on capablilities reported by the PHY. |
| 85 | * This should work for both copper and fiber. |
| 86 | */ |
| 87 | u16 bmsr; |
| 88 | #if defined(CONFIG_PHY_GIGE) |
| 89 | u16 exsr = 0x0000; |
| 90 | #endif |
| 91 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 92 | miiphy_read (devname, addr, MII_BMSR, &bmsr); |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 93 | |
| 94 | #if defined(CONFIG_PHY_GIGE) |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 95 | if (bmsr & BMSR_ESTATEN) |
| 96 | miiphy_read (devname, addr, MII_ESTATUS, &exsr); |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 97 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 98 | if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) { |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 99 | /* 1000BASE-X */ |
| 100 | u16 anar = 0x0000; |
| 101 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 102 | if (exsr & ESTATUS_1000XF) |
Stefan Roese | 772696c | 2011-01-10 12:56:13 +0100 | [diff] [blame] | 103 | anar |= ADVERTISE_1000XFULL; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 104 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 105 | if (exsr & ESTATUS_1000XH) |
| 106 | anar |= ADVERTISE_1000XHALF; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 107 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 108 | miiphy_write (devname, addr, MII_ADVERTISE, anar); |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 109 | } else |
| 110 | #endif |
| 111 | { |
| 112 | u16 anar, btcr; |
| 113 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 114 | miiphy_read (devname, addr, MII_ADVERTISE, &anar); |
| 115 | anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL | |
| 116 | LPA_100HALF | LPA_10FULL | LPA_10HALF); |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 117 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 118 | miiphy_read (devname, addr, MII_CTRL1000, &btcr); |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 119 | btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); |
| 120 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 121 | if (bmsr & BMSR_100BASE4) |
| 122 | anar |= LPA_100BASE4; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 123 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 124 | if (bmsr & BMSR_100FULL) |
| 125 | anar |= LPA_100FULL; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 126 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 127 | if (bmsr & BMSR_100HALF) |
| 128 | anar |= LPA_100HALF; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 129 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 130 | if (bmsr & BMSR_10FULL) |
| 131 | anar |= LPA_10FULL; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 132 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 133 | if (bmsr & BMSR_10HALF) |
| 134 | anar |= LPA_10HALF; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 135 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 136 | miiphy_write (devname, addr, MII_ADVERTISE, anar); |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 137 | |
| 138 | #if defined(CONFIG_PHY_GIGE) |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 139 | if (exsr & ESTATUS_1000_TFULL) |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 140 | btcr |= PHY_1000BTCR_1000FD; |
| 141 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 142 | if (exsr & ESTATUS_1000_THALF) |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 143 | btcr |= PHY_1000BTCR_1000HD; |
| 144 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 145 | miiphy_write (devname, addr, MII_CTRL1000, btcr); |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 146 | #endif |
| 147 | } |
| 148 | |
| 149 | #else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ |
| 150 | /* |
| 151 | * Set up standard advertisement |
| 152 | */ |
| 153 | u16 adv; |
| 154 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 155 | miiphy_read (devname, addr, MII_ADVERTISE, &adv); |
| 156 | adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF | |
| 157 | LPA_10FULL | LPA_10HALF); |
| 158 | miiphy_write (devname, addr, MII_ADVERTISE, adv); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 159 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 160 | miiphy_read (devname, addr, MII_CTRL1000, &adv); |
Marian Balakowicz | 49d0eee | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 161 | adv |= (0x0300); |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 162 | miiphy_write (devname, addr, MII_CTRL1000, adv); |
Marian Balakowicz | 49d0eee | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 163 | |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 164 | #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ |
| 165 | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 166 | /* Start/Restart aneg */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 167 | miiphy_read (devname, addr, MII_BMCR, &bmcr); |
| 168 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
| 169 | miiphy_write (devname, addr, MII_BMCR, bmcr); |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 170 | |
| 171 | return 0; |
| 172 | } |
| 173 | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 174 | /***********************************************************/ |
| 175 | /* read a phy reg and return the value with a rc */ |
| 176 | /***********************************************************/ |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 177 | /* AMCC_TODO: |
| 178 | * Find out of the choice for the emac for MDIO is from the bridges, |
| 179 | * i.e. ZMII or RGMII as approporiate. If the bridges are not used |
| 180 | * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL] |
| 181 | * used? If so, then this routine below does not apply to the 460EX/GT. |
| 182 | * |
| 183 | * sr: Currently on 460EX only EMAC0 works with MDIO, so we always |
| 184 | * return EMAC0 offset here |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 185 | * vg: For 460EX/460GT if internal GPCS PHY address is specified |
| 186 | * return appropriate EMAC offset |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 187 | */ |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 188 | unsigned int miiphy_getemac_offset(u8 addr) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 189 | { |
Mike Frysinger | a23230c | 2011-10-02 10:01:27 +0000 | [diff] [blame^] | 190 | #if defined(CONFIG_440) && \ |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 191 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ |
Mike Frysinger | a23230c | 2011-10-02 10:01:27 +0000 | [diff] [blame^] | 192 | !defined(CONFIG_460EX) && !defined(CONFIG_460GT) |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 193 | unsigned long zmii; |
| 194 | unsigned long eoffset; |
| 195 | |
| 196 | /* Need to find out which mdi port we're using */ |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 197 | zmii = in_be32((void *)ZMII0_FER); |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 198 | |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 199 | if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 200 | /* using port 0 */ |
| 201 | eoffset = 0; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 202 | |
| 203 | else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 204 | /* using port 1 */ |
| 205 | eoffset = 0x100; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 206 | |
| 207 | else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 208 | /* using port 2 */ |
| 209 | eoffset = 0x400; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 210 | |
| 211 | else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 212 | /* using port 3 */ |
| 213 | eoffset = 0x600; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 214 | |
| 215 | else { |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 216 | /* None of the mdi ports are enabled! */ |
| 217 | /* enable port 0 */ |
| 218 | zmii |= ZMII_FER_MDI << ZMII_FER_V (0); |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 219 | out_be32((void *)ZMII0_FER, zmii); |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 220 | eoffset = 0; |
| 221 | /* need to soft reset port 0 */ |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 222 | zmii = in_be32((void *)EMAC0_MR0); |
| 223 | zmii |= EMAC_MR0_SRST; |
| 224 | out_be32((void *)EMAC0_MR0, zmii); |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | return (eoffset); |
| 228 | #else |
Stefan Roese | 153b3e2 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 229 | |
Mike Frysinger | a23230c | 2011-10-02 10:01:27 +0000 | [diff] [blame^] | 230 | #if defined(CONFIG_405EX) |
Stefan Roese | 153b3e2 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 231 | unsigned long rgmii; |
| 232 | int devnum = 1; |
| 233 | |
Stefan Roese | 69710095 | 2007-10-23 14:03:17 +0200 | [diff] [blame] | 234 | rgmii = in_be32((void *)RGMII_FER); |
Stefan Roese | 153b3e2 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 235 | if (rgmii & (1 << (19 - devnum))) |
| 236 | return 0x100; |
| 237 | #endif |
| 238 | |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 239 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 240 | u32 eoffset = 0; |
| 241 | |
| 242 | switch (addr) { |
| 243 | #if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR) |
| 244 | case CONFIG_GPCS_PHY1_ADDR: |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 245 | if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100))) |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 246 | eoffset = 0x100; |
| 247 | break; |
| 248 | #endif |
| 249 | #if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR) |
| 250 | case CONFIG_GPCS_PHY2_ADDR: |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 251 | if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300))) |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 252 | eoffset = 0x300; |
| 253 | break; |
| 254 | #endif |
| 255 | #if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR) |
| 256 | case CONFIG_GPCS_PHY3_ADDR: |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 257 | if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400))) |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 258 | eoffset = 0x400; |
| 259 | break; |
| 260 | #endif |
| 261 | default: |
| 262 | eoffset = 0; |
| 263 | break; |
| 264 | } |
| 265 | return eoffset; |
| 266 | #endif |
| 267 | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 268 | return 0; |
| 269 | #endif |
| 270 | } |
| 271 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 272 | static int emac_miiphy_wait(u32 emac_reg) |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 273 | { |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 274 | u32 sta_reg; |
| 275 | int i; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 276 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 277 | /* wait for completion */ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 278 | i = 0; |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 279 | do { |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 280 | sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 281 | if (i++ > 5) { |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 282 | debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__, |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 283 | __LINE__, sta_reg); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 284 | return -1; |
| 285 | } |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 286 | udelay(10); |
| 287 | } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK); |
| 288 | |
| 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) |
| 293 | { |
| 294 | u32 emac_reg; |
| 295 | u32 sta_reg; |
| 296 | |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 297 | emac_reg = miiphy_getemac_offset(addr); |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 298 | |
| 299 | /* wait for completion */ |
| 300 | if (emac_miiphy_wait(emac_reg) != 0) |
| 301 | return -1; |
| 302 | |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 303 | sta_reg = reg; /* reg address */ |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 304 | |
Wolfgang Denk | af0501a | 2008-10-19 02:35:50 +0200 | [diff] [blame] | 305 | /* set clock (50MHz) and read flags */ |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 306 | #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ |
Stefan Roese | 153b3e2 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 307 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 308 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
Stefan Roese | 153b3e2 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 309 | defined(CONFIG_405EX) |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 310 | #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 311 | sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd; |
Marian Balakowicz | 49d0eee | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 312 | #else |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 313 | sta_reg |= cmd; |
Marian Balakowicz | 49d0eee | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 314 | #endif |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 315 | #else |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 316 | sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ; |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 317 | #endif |
| 318 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 319 | /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */ |
wdenk | 232fe0b | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 320 | sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 321 | sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */ |
Marian Balakowicz | 49d0eee | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 322 | sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 323 | if (cmd == EMAC_STACR_WRITE) |
| 324 | memcpy(&sta_reg, &value, 2); /* put in data */ |
| 325 | |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 326 | out_be32((void *)EMAC0_STACR + emac_reg, sta_reg); |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 327 | debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 328 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 329 | /* wait for completion */ |
| 330 | if (emac_miiphy_wait(emac_reg) != 0) |
| 331 | return -1; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 332 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 333 | debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 334 | if ((sta_reg & EMAC_STACR_PHYE) != 0) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 335 | return -1; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 336 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 337 | return 0; |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 338 | } |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 339 | |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 340 | int emac4xx_miiphy_read (const char *devname, unsigned char addr, unsigned char reg, |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 341 | unsigned short *value) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 342 | { |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 343 | unsigned long sta_reg; |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 344 | unsigned long emac_reg; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 345 | |
Victor Gallardo | 45a06ff | 2008-09-04 23:49:36 -0700 | [diff] [blame] | 346 | emac_reg = miiphy_getemac_offset(addr); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 347 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 348 | if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0) |
| 349 | return -1; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 350 | |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 351 | sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); |
Stefan Roese | 1fc08dd | 2009-09-07 10:52:24 +0200 | [diff] [blame] | 352 | *value = sta_reg >> 16; |
Larry Johnson | 50325a0 | 2007-12-27 10:50:55 -0500 | [diff] [blame] | 353 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 354 | return 0; |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 355 | } |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 356 | |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 357 | /***********************************************************/ |
| 358 | /* write a phy reg and return the value with a rc */ |
| 359 | /***********************************************************/ |
| 360 | |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 361 | int emac4xx_miiphy_write (const char *devname, unsigned char addr, unsigned char reg, |
Stefan Roese | 8b231b2 | 2008-02-19 21:58:25 +0100 | [diff] [blame] | 362 | unsigned short value) |
| 363 | { |
| 364 | return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value); |
| 365 | } |