Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a1fa5cbbc00b663f074408045fc0460b0d04603d / . / board / phytec / common / k3 / Kconfig
blob: 282f4b7974290ec113ed95ab7f35a752908a53d5 [file] [log] [blame]
Garrett Giordano39b1bef2024-11-12 12:40:23 -0800[diff] [blame]1config PHYTEC_K3_DDR_PATCH
2 bool "Patch DDR timings on PHYTEC K3 SoMs"
3 help
4 Allow to override default DDR timings prior to
5 DDRSS driver probing.