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git01.mediatek.com / filogic / uboot / a18db1dd8345842eb87495e36f17961fa5637a7b / . / arch / arm / dts / fsl-ls1088a.dtsi
blob: 72d755a18cefaba03a38c931a0cf63458e4d810f [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Ashish Kumarb25faa22017-08-31 16:12:53 +0530[diff] [blame]2/*
3 * NXP ls1088a SOC common device tree source
4 *
5 * Copyright 2017 NXP
Ashish Kumarb25faa22017-08-31 16:12:53 +0530[diff] [blame]6 */
7
8/ {
9 compatible = "fsl,ls1088a";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 memory@80000000 {
15 device_type = "memory";
16 reg = <0x00000000 0x80000000 0 0x80000000>;
17 /* DRAM space - 1, size : 2 GB DRAM */
18 };
19
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
24 #interrupt-cells = <3>;
25 interrupt-controller;
26 interrupts = <1 9 0x4>;
27 };
28
29 timer {
30 compatible = "arm,armv8-timer";
31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
35 };
36
37 serial0: serial@21c0500 {
38 device_type = "serial";
39 compatible = "fsl,ns16550", "ns16550a";
40 reg = <0x0 0x21c0500 0x0 0x100>;
41 clock-frequency = <0>; /* Updated by bootloader */
42 interrupts = <0 32 0x1>; /* edge triggered */
43 };
44
45 serial1: serial@21c0600 {
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550a";
48 reg = <0x0 0x21c0600 0x0 0x100>;
49 clock-frequency = <0>; /* Updated by bootloader */
50 interrupts = <0 32 0x1>; /* edge triggered */
51 };
52
53 fsl_mc: fsl-mc@80c000000 {
54 compatible = "fsl,qoriq-mc";
55 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
56 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
57 };
58
59 dspi: dspi@2100000 {
60 compatible = "fsl,vf610-dspi";
61 #address-cells = <1>;
62 #size-cells = <0>;
63 reg = <0x0 0x2100000 0x0 0x10000>;
64 interrupts = <0 26 0x4>; /* Level high type */
65 num-cs = <6>;
66 };
67
68 qspi: quadspi@1550000 {
69 compatible = "fsl,vf610-qspi";
70 #address-cells = <1>;
71 #size-cells = <0>;
72 reg = <0x0 0x20c0000 0x0 0x10000>,
73 <0x0 0x20000000 0x0 0x10000000>;
74 reg-names = "QuadSPI", "QuadSPI-memory";
75 num-cs = <4>;
76 };
Yinbo Zhu26caa0e2018-09-25 14:47:09 +0800[diff] [blame]77
78 esdhc: esdhc@2140000 {
79 compatible = "fsl,esdhc";
80 reg = <0x0 0x2140000 0x0 0x10000>;
81 interrupts = <0 28 0x4>; /* Level high type */
82 little-endian;
83 bus-width = <4>;
84 };
85
Ashish Kumar55fd8b92018-02-19 14:16:58 +0530[diff] [blame]86 ifc: ifc@1530000 {
87 compatible = "fsl,ifc", "simple-bus";
88 reg = <0x0 0x2240000 0x0 0x20000>;
89 interrupts = <0 21 0x4>; /* Level high type */
90 };
Hou Zhiqiang6ae9a8c2017-09-04 10:47:53 +0800[diff] [blame]91
Ran Wang9a43a6c2017-10-23 10:09:24 +0800[diff] [blame]92 usb0: usb3@3100000 {
93 compatible = "fsl,layerscape-dwc3";
94 reg = <0x0 0x3100000 0x0 0x10000>;
95 interrupts = <0 80 0x4>; /* Level high type */
96 dr_mode = "host";
97 };
98
99 usb1: usb3@3110000 {
100 compatible = "fsl,layerscape-dwc3";
101 reg = <0x0 0x3110000 0x0 0x10000>;
102 interrupts = <0 81 0x4>; /* Level high type */
103 dr_mode = "host";
104 };
105
Hou Zhiqiang6ae9a8c2017-09-04 10:47:53 +0800[diff] [blame]106 pcie@3400000 {
107 compatible = "fsl,ls-pcie", "snps,dw-pcie";
108 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
109 0x00 0x03480000 0x0 0x80000 /* lut registers */
110 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
111 0x20 0x00000000 0x0 0x20000>; /* configuration space */
112 reg-names = "dbi", "lut", "ctrl", "config";
113 #address-cells = <3>;
114 #size-cells = <2>;
115 device_type = "pci";
116 num-lanes = <4>;
117 bus-range = <0x0 0xff>;
118 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
119 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
120 };
121
122 pcie@3500000 {
123 compatible = "fsl,ls-pcie", "snps,dw-pcie";
124 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
125 0x00 0x03580000 0x0 0x80000 /* lut registers */
126 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
127 0x28 0x00000000 0x0 0x20000>; /* configuration space */
128 reg-names = "dbi", "lut", "ctrl", "config";
129 #address-cells = <3>;
130 #size-cells = <2>;
131 device_type = "pci";
132 num-lanes = <4>;
133 bus-range = <0x0 0xff>;
134 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
135 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
136 };
137
138 pcie@3600000 {
139 compatible = "fsl,ls-pcie", "snps,dw-pcie";
140 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
141 0x00 0x03680000 0x0 0x80000 /* lut registers */
142 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
143 0x30 0x00000000 0x0 0x20000>; /* configuration space */
144 reg-names = "dbi", "lut", "ctrl", "config";
145 #address-cells = <3>;
146 #size-cells = <2>;
147 device_type = "pci";
148 num-lanes = <8>;
149 bus-range = <0x0 0xff>;
150 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
151 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
152 };
Ashish Kumarb25faa22017-08-31 16:12:53 +0530[diff] [blame]153};