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git01.mediatek.com / filogic / uboot / a03cb92688346145a51229f3467fe208c0ad6d9e / . / dts / upstream / Bindings / net / can / xilinx,can.yaml
blob: 40835497050a5effd191a956b41cea7b33ce36a4 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title:
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]8 Xilinx CAN and CANFD controller
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]9
10maintainers:
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
12
13properties:
14 compatible:
15 enum:
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
20
21 reg:
22 maxItems: 1
23
24 interrupts:
25 maxItems: 1
26
27 clocks:
28 minItems: 1
29 maxItems: 2
30
31 clock-names:
32 maxItems: 2
33
34 power-domains:
35 maxItems: 1
36
37 tx-fifo-depth:
38 $ref: /schemas/types.yaml#/definitions/uint32
39 description: CAN Tx fifo depth (Zynq, Axi CAN).
40
41 rx-fifo-depth:
42 $ref: /schemas/types.yaml#/definitions/uint32
43 description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
44
45 tx-mailbox-count:
46 $ref: /schemas/types.yaml#/definitions/uint32
47 description: CAN Tx mailbox buffer count (CAN FD)
48
49 resets:
50 maxItems: 1
51
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]52 xlnx,has-ecc:
53 $ref: /schemas/types.yaml#/definitions/flag
54 description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN)
55
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]56required:
57 - compatible
58 - reg
59 - interrupts
60 - clocks
61 - clock-names
62
63unevaluatedProperties: false
64
65allOf:
66 - $ref: can-controller.yaml#
67 - if:
68 properties:
69 compatible:
70 contains:
71 enum:
72 - xlnx,zynq-can-1.0
73
74 then:
75 properties:
76 clock-names:
77 items:
78 - const: can_clk
79 - const: pclk
80 required:
81 - tx-fifo-depth
82 - rx-fifo-depth
83
84 - if:
85 properties:
86 compatible:
87 contains:
88 enum:
89 - xlnx,axi-can-1.00.a
90
91 then:
92 properties:
93 clock-names:
94 items:
95 - const: can_clk
96 - const: s_axi_aclk
97 required:
98 - tx-fifo-depth
99 - rx-fifo-depth
100
101 - if:
102 properties:
103 compatible:
104 contains:
105 enum:
106 - xlnx,canfd-1.0
107 - xlnx,canfd-2.0
108
109 then:
110 properties:
111 clock-names:
112 items:
113 - const: can_clk
114 - const: s_axi_aclk
115 required:
116 - tx-mailbox-count
117 - rx-fifo-depth
118
119examples:
120 - |
121 #include <dt-bindings/interrupt-controller/arm-gic.h>
122
123 can@e0008000 {
124 compatible = "xlnx,zynq-can-1.0";
125 reg = <0xe0008000 0x1000>;
126 clocks = <&clkc 19>, <&clkc 36>;
127 clock-names = "can_clk", "pclk";
128 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-parent = <&intc>;
130 tx-fifo-depth = <0x40>;
131 rx-fifo-depth = <0x40>;
132 };
133
134 - |
135 can@40000000 {
136 compatible = "xlnx,axi-can-1.00.a";
137 reg = <0x40000000 0x10000>;
138 clocks = <&clkc 0>, <&clkc 1>;
139 clock-names = "can_clk", "s_axi_aclk";
140 interrupt-parent = <&intc>;
141 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
142 tx-fifo-depth = <0x40>;
143 rx-fifo-depth = <0x40>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]144 xlnx,has-ecc;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]145 };
146
147 - |
148 can@40000000 {
149 compatible = "xlnx,canfd-1.0";
150 reg = <0x40000000 0x2000>;
151 clocks = <&clkc 0>, <&clkc 1>;
152 clock-names = "can_clk", "s_axi_aclk";
153 interrupt-parent = <&intc>;
154 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
155 tx-mailbox-count = <0x20>;
156 rx-fifo-depth = <0x20>;
157 };
158
159 - |
160 can@ff060000 {
161 compatible = "xlnx,canfd-2.0";
162 reg = <0xff060000 0x6000>;
163 clocks = <&clkc 0>, <&clkc 1>;
164 clock-names = "can_clk", "s_axi_aclk";
165 interrupt-parent = <&intc>;
166 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
167 tx-mailbox-count = <0x20>;
168 rx-fifo-depth = <0x40>;
169 };