| Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Spreadtrum SC9860 clock |
| 8 | |
| 9 | maintainers: |
| 10 | - Orson Zhai <orsonzhai@gmail.com> |
| 11 | - Baolin Wang <baolin.wang7@gmail.com> |
| 12 | - Chunyan Zhang <zhang.lyra@gmail.com> |
| 13 | |
| 14 | properties: |
| 15 | compatible: |
| 16 | enum: |
| 17 | - sprd,sc9860-agcp-gate |
| 18 | - sprd,sc9860-aonsecure-clk |
| 19 | - sprd,sc9860-aon-gate |
| 20 | - sprd,sc9860-aon-prediv |
| 21 | - sprd,sc9860-apahb-gate |
| 22 | - sprd,sc9860-apapb-gate |
| 23 | - sprd,sc9860-ap-clk |
| 24 | - sprd,sc9860-cam-clk |
| 25 | - sprd,sc9860-cam-gate |
| 26 | - sprd,sc9860-disp-clk |
| 27 | - sprd,sc9860-disp-gate |
| 28 | - sprd,sc9860-gpu-clk |
| 29 | - sprd,sc9860-pll |
| 30 | - sprd,sc9860-pmu-gate |
| 31 | - sprd,sc9860-vsp-clk |
| 32 | - sprd,sc9860-vsp-gate |
| 33 | |
| 34 | reg: |
| 35 | maxItems: 1 |
| 36 | |
| 37 | clocks: |
| 38 | minItems: 1 |
| 39 | maxItems: 3 |
| 40 | |
| 41 | '#clock-cells': |
| 42 | const: 1 |
| 43 | |
| 44 | sprd,syscon: |
| 45 | $ref: /schemas/types.yaml#/definitions/phandle |
| 46 | description: |
| 47 | phandle to the syscon which is in the same address area with the |
| 48 | clock, and so we can get regmap for the clocks from the syscon device |
| 49 | |
| 50 | required: |
| 51 | - compatible |
| 52 | - clocks |
| 53 | - '#clock-cells' |
| 54 | |
| 55 | allOf: |
| 56 | - if: |
| 57 | properties: |
| 58 | compatible: |
| 59 | contains: |
| 60 | enum: |
| 61 | - sprd,sc9860-agcp-gate |
| 62 | - sprd,sc9860-aon-gate |
| 63 | - sprd,sc9860-apahb-gate |
| 64 | - sprd,sc9860-apapb-gate |
| 65 | - sprd,sc9860-cam-gate |
| 66 | - sprd,sc9860-disp-gate |
| 67 | - sprd,sc9860-gpu-clk |
| 68 | - sprd,sc9860-pll |
| 69 | - sprd,sc9860-pmu-gate |
| 70 | - sprd,sc9860-vsp-gate |
| 71 | then: |
| 72 | properties: |
| 73 | clocks: |
| 74 | maxItems: 1 |
| 75 | - if: |
| 76 | properties: |
| 77 | compatible: |
| 78 | contains: |
| 79 | enum: |
| 80 | - sprd,sc9860-aonsecure-clk |
| 81 | - sprd,sc9860-cam-clk |
| 82 | - sprd,sc9860-disp-clk |
| 83 | - sprd,sc9860-vsp-clk |
| 84 | then: |
| 85 | properties: |
| 86 | clocks: |
| 87 | minItems: 2 |
| 88 | maxItems: 2 |
| 89 | - if: |
| 90 | properties: |
| 91 | compatible: |
| 92 | contains: |
| 93 | enum: |
| 94 | - sprd,sc9860-aon-prediv |
| 95 | - sprd,sc9860-ap-clk |
| 96 | then: |
| 97 | properties: |
| 98 | clocks: |
| 99 | minItems: 3 |
| 100 | - if: |
| 101 | properties: |
| 102 | compatible: |
| 103 | contains: |
| 104 | enum: |
| 105 | - sprd,sc9860-aonsecure-clk |
| 106 | - sprd,sc9860-aon-prediv |
| 107 | - sprd,sc9860-ap-clk |
| 108 | - sprd,sc9860-cam-clk |
| 109 | - sprd,sc9860-disp-clk |
| 110 | - sprd,sc9860-gpu-clk |
| 111 | - sprd,sc9860-vsp-clk |
| 112 | then: |
| 113 | required: |
| 114 | - reg |
| 115 | properties: |
| 116 | sprd,syscon: false |
| 117 | - if: |
| 118 | properties: |
| 119 | compatible: |
| 120 | contains: |
| 121 | enum: |
| 122 | - sprd,sc9860-agcp-gate |
| 123 | - sprd,sc9860-aon-gate |
| 124 | - sprd,sc9860-apahb-gate |
| 125 | - sprd,sc9860-apapb-gate |
| 126 | - sprd,sc9860-cam-gate |
| 127 | - sprd,sc9860-disp-gate |
| 128 | - sprd,sc9860-pll |
| 129 | - sprd,sc9860-pmu-gate |
| 130 | - sprd,sc9860-vsp-gate |
| 131 | then: |
| 132 | required: |
| 133 | - sprd,syscon |
| 134 | properties: |
| 135 | reg: false |
| 136 | |
| 137 | additionalProperties: false |
| 138 | |
| 139 | examples: |
| 140 | - | |
| 141 | soc { |
| 142 | #address-cells = <2>; |
| 143 | #size-cells = <2>; |
| 144 | |
| 145 | pmu-gate { |
| 146 | compatible = "sprd,sc9860-pmu-gate"; |
| 147 | clocks = <&ext_26m>; |
| 148 | #clock-cells = <1>; |
| 149 | sprd,syscon = <&pmu_regs>; |
| 150 | }; |
| 151 | |
| 152 | clock-controller@20000000 { |
| 153 | compatible = "sprd,sc9860-ap-clk"; |
| 154 | reg = <0 0x20000000 0 0x400>; |
| 155 | clocks = <&ext_26m>, <&pll 0>, <&pmu_gate 0>; |
| 156 | #clock-cells = <1>; |
| 157 | }; |
| 158 | }; |
| 159 | ... |