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git01.mediatek.com / filogic / uboot / 9fe526db6e1dde0a8710a5c08aedb86dd02693b4 / . / arch / arm / dts / fsl-imx8qm-apalis.dts
blob: e089ddb8468a5fb87602e4fc29e67d0cfe635d54 [file] [log] [blame]
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2017-2019 Toradex
4 */
5
6/dts-v1/;
7
8/* First 128KB is for PSCI ATF. */
9/memreserve/ 0x80000000 0x00020000;
10
11#include "fsl-imx8qm.dtsi"
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]12
13/ {
Philippe Schenkerc3144042020-08-28 21:08:06 +0300[diff] [blame]14 model = "Toradex Apalis iMX8";
15 compatible = "toradex,apalis-imx8", "fsl,imx8qm";
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]16
17 chosen {
18 bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
19 stdout-path = &lpuart1;
20 };
21};
22
23&iomuxc {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
26 <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
27 <&pinctrl_gpio12>, <&pinctrl_gpio34>, <&pinctrl_gpio56>,
28 <&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_gpio_bkl_on>,
29 <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>,
30 <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>,
31 <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>,
32 <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>,
33 <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>,
34 <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
35 <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
36 <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
37 <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
38 <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>;
39
Philippe Schenkerc3144042020-08-28 21:08:06 +0300[diff] [blame]40 apalis-imx8 {
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]41 pinctrl_gpio12: gpio12grp {
42 fsl,pins = <
43 /* Apalis GPIO1 */
44 SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021
45 /* Apalis GPIO2 */
46 SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021
47 >;
48 };
49
50 pinctrl_gpio34: gpio34grp {
51 fsl,pins = <
52 /* Apalis GPIO3 */
53 SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021
54 /* Apalis GPIO4 */
55 SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021
56 >;
57 };
58
59 pinctrl_gpio56: gpio56grp {
60 fsl,pins = <
61 /* Apalis GPIO5 */
62 SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021
63 /* Apalis GPIO6 */
64 SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000021
65 >;
66 };
67
68 pinctrl_gpio7: gpio7 {
69 fsl,pins = <
70 /* Apalis GPIO7 */
71 SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021
72 >;
73 };
74
75 pinctrl_gpio8: gpio8 {
76 fsl,pins = <
77 /* Apalis GPIO8 */
78 SC_P_MLB_DATA_LSIO_GPIO3_IO28 0x00000021
79 >;
80 };
81
82 pinctrl_gpio_keys: gpio-keys {
83 fsl,pins = <
84 /* Apalis WAKE1_MICO */
85 SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x06000021
86 >;
87 };
88
89 pinctrl_fec1: fec1grp {
90 fsl,pins = <
91 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */
92 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
93 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
94 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
95 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
96 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
97 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
98 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
99 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
100 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
101 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
102 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
103 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
104 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
105 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
106 SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020
107 /* ETH_RESET# */
108 SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020
109 >;
110 };
111
112 pinctrl_gpio_bkl_on: gpio-bkl-on {
113 fsl,pins = <
114 /* Apalis BKL_ON */
115 SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021
116 >;
117 };
118
119 /* Apalis I2C2 (DDC) */
120 pinctrl_lpi2c0: lpi2c0grp {
121 fsl,pins = <
122 SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022
123 SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022
124 >;
125 };
126
127 pinctrl_cam1_gpios: cam1gpiosgrp {
128 fsl,pins = <
129 /* Apalis CAM1_D7 */
130 SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021
131 /* Apalis CAM1_D6 */
132 SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021
133 /* Apalis CAM1_D5 */
134 SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021
135 /* Apalis CAM1_D4 */
136 SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021
137 /* Apalis CAM1_D3 */
138 SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021
139 /* Apalis CAM1_D2 */
140 SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021
141 /* Apalis CAM1_D1 */
142 SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021
143 /* Apalis CAM1_D0 */
144 SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021
145 /* Apalis CAM1_PCLK */
146 SC_P_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021
147 /* Apalis CAM1_MCLK */
148 SC_P_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021
149 /* Apalis CAM1_VSYNC */
150 SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021
151 /* Apalis CAM1_HSYNC */
152 SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021
153 >;
154 };
155
156 pinctrl_dap1_gpios: dap1gpiosgrp {
157 fsl,pins = <
158 /* Apalis DAP1_MCLK */
159 SC_P_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021
160 /* Apalis DAP1_D_OUT */
161 SC_P_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021
162 /* Apalis DAP1_RESET */
163 SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
164 /* Apalis DAP1_BIT_CLK */
165 SC_P_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021
166 /* Apalis DAP1_D_IN */
167 SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021
168 /* Apalis DAP1_SYNC */
169 SC_P_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021
170 /* Wi-Fi_I2S_EN# */
171 SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021
172 >;
173 };
174
175 pinctrl_esai0_gpios: esai0gpiosgrp {
176 fsl,pins = <
177 /* Apalis LCD1_G1 */
178 SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021
179 /* Apalis LCD1_G2 */
180 SC_P_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021
181 >;
182 };
183
184 pinctrl_fec2_gpios: fec2gpiosgrp {
185 fsl,pins = <
186 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
187 /* Apalis LCD1_R1 */
188 SC_P_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021
189 /* Apalis LCD1_R0 */
190 SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021
191 /* Apalis LCD1_G0 */
192 SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021
193 /* Apalis LCD1_R7 */
194 SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021
195 /* Apalis LCD1_DE */
196 SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021
197 /* Apalis LCD1_HSYNC */
198 SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021
199 /* Apalis LCD1_VSYNC */
200 SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021
201 /* Apalis LCD1_PCLK */
202 SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021
203 /* Apalis LCD1_R6 */
204 SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021
205 /* Apalis LCD1_R5 */
206 SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021
207 /* Apalis LCD1_R4 */
208 SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021
209 /* Apalis LCD1_R3 */
210 SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021
211 /* Apalis LCD1_R2 */
212 SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021
213 >;
214 };
215
216 pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio {
217 fsl,pins = <
218 /* Apalis TS_2 */
219 SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021
220 >;
221 };
222
223 pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
224 fsl,pins = <
225 /* Apalis LCD1_G6 */
226 SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021
227 /* Apalis LCD1_G7 */
228 SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021
229 >;
230 };
231
232 pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
233 fsl,pins = <
234 /* Apalis TS_4 */
235 SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021
236 >;
237 };
238
239 pinctrl_mlb_gpios: mlbgpiosgrp {
240 fsl,pins = <
241 /* Apalis TS_1 */
242 SC_P_MLB_CLK_LSIO_GPIO3_IO27 0x00000021
243 >;
244 };
245
246 pinctrl_qspi1a_gpios: qspi1agpiosgrp {
247 fsl,pins = <
248 /* Apalis LCD1_B0 */
249 SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
250 /* Apalis LCD1_B1 */
251 SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021
252 /* Apalis LCD1_B2 */
253 SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021
254 /* Apalis LCD1_B3 */
255 SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021
256 /* Apalis LCD1_B5 */
257 SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021
258 /* Apalis LCD1_B7 */
259 SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021
260 /* Apalis LCD1_B4 */
261 SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021
262 /* Apalis LCD1_B6 */
263 SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021
264 >;
265 };
266
267 pinctrl_sim0_gpios: sim0gpiosgrp {
268 fsl,pins = <
269 /* Apalis LCD1_G5 */
270 SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021
271 /* Apalis LCD1_G3 */
272 SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021
273 /* Apalis TS_5 */
274 SC_P_SIM0_IO_LSIO_GPIO0_IO02 0x00000021
275 /* Apalis LCD1_G4 */
276 SC_P_SIM0_RST_LSIO_GPIO0_IO01 0x00000021
277 >;
278 };
279
280 pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
281 fsl,pins = <
282 /* Apalis TS_6 */
283 SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021
284 >;
285 };
286
287 pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en {
288 fsl,pins = <
289 /* Apalis TS_3 */
290 SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021
291 >;
292 };
293
294 /* On-module I2C */
295 pinctrl_lpi2c1: lpi2c1grp {
296 fsl,pins = <
297 SC_P_GPT0_CLK_DMA_I2C1_SCL 0x04000020
298 SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020
299 >;
300 };
301
302 /* Apalis I2C1 */
303 pinctrl_lpi2c2: lpi2c2grp {
304 fsl,pins = <
305 SC_P_GPT1_CLK_DMA_I2C2_SCL 0x04000020
306 SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020
307 >;
308 };
309
310 /* Apalis I2C3 (CAM) */
311 pinctrl_lpi2c3: lpi2c3grp {
312 fsl,pins = <
313 SC_P_SIM0_PD_DMA_I2C3_SCL 0x04000020
314 SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020
315 >;
316 };
317
318 /* Apalis UART3 */
319 pinctrl_lpuart0: lpuart0grp {
320 fsl,pins = <
321 SC_P_UART0_RX_DMA_UART0_RX 0x06000020
322 SC_P_UART0_TX_DMA_UART0_TX 0x06000020
323 >;
324 };
325
326 /* Apalis UART1 */
327 pinctrl_lpuart1: lpuart1grp {
328 fsl,pins = <
329 SC_P_UART1_RX_DMA_UART1_RX 0x06000020
330 SC_P_UART1_TX_DMA_UART1_TX 0x06000020
331 SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
332 SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
333 >;
334 };
335
336 pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
337 fsl,pins = <
338 /* Apalis UART1_DTR */
339 SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021
340 /* Apalis UART1_DSR */
341 SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021
342 /* Apalis UART1_DCD */
343 SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021
344 /* Apalis UART1_RI */
345 SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021
346 >;
347 };
348
349 /* Apalis UART4 */
350 pinctrl_lpuart2: lpuart2grp {
351 fsl,pins = <
352 SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020
353 SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020
354 >;
355 };
356
357 /* Apalis UART2 */
358 pinctrl_lpuart3: lpuart3grp {
359 fsl,pins = <
360 SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020
361 SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020
362 SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020
363 SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020
364 >;
365 };
366
367 /* Apalis PWM3 */
368 pinctrl_gpio_pwm0: gpiopwm0grp {
369 fsl,pins = <
370 SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 0x00000021
371 >;
372 };
373
374 /* Apalis PWM4 */
375 pinctrl_gpio_pwm1: gpiopwm1grp {
376 fsl,pins = <
377 SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 0x00000021
378 >;
379 };
380
381 /* Apalis PWM1 */
382 pinctrl_gpio_pwm2: gpiopwm2grp {
383 fsl,pins = <
384 SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 0x00000021
385 >;
386 };
387
388 /* Apalis PWM2 */
389 pinctrl_gpio_pwm3: gpiopwm3grp {
390 fsl,pins = <
391 SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 0x00000021
392 >;
393 };
394
395 /* Apalis BKL1_PWM */
396 pinctrl_gpio_pwm_bkl: gpiopwmbklgrp {
397 fsl,pins = <
398 SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 0x00000021
399 >;
400 };
401
402 /* Apalis USBH_EN */
403 pinctrl_gpio_usbh_en: gpiousbhen {
404 fsl,pins = <
405 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x06000060
406 >;
407 };
408
409 /* Apalis USBH_OC# */
410 pinctrl_gpio_usbh_oc_n: gpiousbhocn {
411 fsl,pins = <
412 SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000060
413 >;
414 };
415
416 /* Apalis USBO1_EN */
417 pinctrl_gpio_usbo1_en: gpiousbo1en {
418 fsl,pins = <
419 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000060
420 >;
421 };
422
423 /* Apalis USBO1_OC# */
424 pinctrl_gpio_usbo1_oc_n: gpiousbo1ocn {
425 fsl,pins = <
426 SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x06000060
427 >;
428 };
429
430 pinctrl_usdhc1: usdhc1grp {
431 fsl,pins = <
432 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
433 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
434 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
435 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
436 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
437 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
438 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
439 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
440 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
441 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
442 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
443 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
444 >;
445 };
446
447 pinctrl_sata1_act: sata1actgrp {
448 fsl,pins = <
449 /* Apalis SATA1_ACT# */
450 SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
451 >;
452 };
453
454 pinctrl_mmc1_cd: mmc1cdgrp {
455 fsl,pins = <
456 /* Apalis MMC1_CD# */
457 SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
458 >;
459 };
460
461 pinctrl_usdhc2: usdhc2grp {
462 fsl,pins = <
463 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
464 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
465 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
466 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
467 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
468 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
469 SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021
470 SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021
471 SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021
472 SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021
473 /* On-module PMIC use */
474 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
475 >;
476 };
477
478 pinctrl_sd1_cd: sd1cdgrp {
479 fsl,pins = <
480 /* Apalis SD1_CD# */
481 SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
482 >;
483 };
484
485 pinctrl_usdhc3: usdhc3grp {
486 fsl,pins = <
487 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
488 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
489 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
490 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
491 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
492 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
493 /* On-module PMIC use */
494 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
495 >;
496 };
497 };
498};
499
500&fec1 {
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_fec1>;
503 fsl,magic-packet;
504 phy-handle = <&ethphy0>;
Oleksandr Suvorov6d035112021-02-09 10:38:13 +0200[diff] [blame]505 phy-mode = "rgmii-id";
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]506 phy-reset-duration = <10>;
507 phy-reset-gpios = <&gpio1 11 1>;
508 status = "okay";
509
510 mdio {
511 #address-cells = <1>;
512 #size-cells = <0>;
513
514 ethphy0: ethernet-phy@7 {
515 compatible = "ethernet-phy-ieee802.3-c22";
516 reg = <7>;
517 };
518 };
519};
520
521/* Apalis I2C2 (DDC) */
522&i2c0 {
523 #address-cells = <1>;
524 #size-cells = <0>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_lpi2c0>;
527 clock-frequency = <100000>;
528 status = "okay";
529};
530
531/* On-module I2C */
532&i2c1 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 clock-frequency = <100000>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_lpi2c1>;
538 status = "okay";
539};
540
541/* Apalis I2C1 */
542&i2c2 {
543 #address-cells = <1>;
544 #size-cells = <0>;
545 clock-frequency = <100000>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_lpi2c2>;
548 status = "okay";
549};
550
551/* Apalis I2C3 (CAM) */
552&i2c3 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 clock-frequency = <100000>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_lpi2c3>;
558 status = "okay";
559};
560
561/* Apalis UART3 */
562&lpuart0 {
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_lpuart0>;
565 status = "okay";
566};
567
568/* Apalis UART1 */
569&lpuart1 {
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_lpuart1>;
572 status = "okay";
573};
574
575/* Apalis UART4 */
576&lpuart2 {
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_lpuart2>;
579 status = "okay";
580};
581
582/* Apalis UART2 */
583&lpuart3 {
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_lpuart3>;
586 status = "okay";
587};
588
589/* eMMC */
590&usdhc1 {
Andrejs Cainikovscde1ac62023-01-16 20:05:15 +0100[diff] [blame]591 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]592 pinctrl-0 = <&pinctrl_usdhc1>;
Andrejs Cainikovscde1ac62023-01-16 20:05:15 +0100[diff] [blame]593 pinctrl-1 = <&pinctrl_usdhc1>;
594 pinctrl-2 = <&pinctrl_usdhc1>;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]595 bus-width = <8>;
596 non-removable;
597 status = "okay";
598};
599
600/* Apalis MMC1 */
601&usdhc2 {
Andrejs Cainikovscde1ac62023-01-16 20:05:15 +0100[diff] [blame]602 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]603 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
Andrejs Cainikovscde1ac62023-01-16 20:05:15 +0100[diff] [blame]604 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
605 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]606 bus-width = <8>;
607 cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
608 status = "okay";
609};
610
611/* Apalis SD1 */
612&usdhc3 {
613 pinctrl-names = "default";
614 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
615 bus-width = <4>;
616 cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
617 status = "okay";
618};