blob: b71cbfcc0b0a530981a399952e657fbf0b1a7827 [file] [log] [blame]
Neil Armstrongadd986c2018-07-24 17:45:28 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Amlogic Meson Video Processing Unit driver
4 *
5 * Copyright (c) 2018 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 */
8
9#include "meson_vpu.h"
10
11/* DMC Registers */
12#define DMC_CAV_LUT_DATAL 0x48 /* 0x12 offset in data sheet */
13#define CANVAS_WIDTH_LBIT 29
14#define CANVAS_WIDTH_LWID 3
15#define DMC_CAV_LUT_DATAH 0x4c /* 0x13 offset in data sheet */
16#define CANVAS_WIDTH_HBIT 0
17#define CANVAS_HEIGHT_BIT 9
18#define CANVAS_BLKMODE_BIT 24
19#define DMC_CAV_LUT_ADDR 0x50 /* 0x14 offset in data sheet */
20#define CANVAS_LUT_WR_EN (0x2 << 8)
21#define CANVAS_LUT_RD_EN (0x1 << 8)
22
23void meson_canvas_setup(struct meson_vpu_priv *priv,
24 u32 canvas_index, u32 addr,
25 u32 stride, u32 height,
26 unsigned int wrap,
27 unsigned int blkmode)
28{
29 dmc_write(DMC_CAV_LUT_DATAL,
30 (((addr + 7) >> 3)) |
31 (((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
32
33 dmc_write(DMC_CAV_LUT_DATAH,
34 ((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) <<
35 CANVAS_WIDTH_HBIT) |
36 (height << CANVAS_HEIGHT_BIT) |
37 (wrap << 22) |
38 (blkmode << CANVAS_BLKMODE_BIT));
39
40 dmc_write(DMC_CAV_LUT_ADDR,
41 CANVAS_LUT_WR_EN | canvas_index);
42
43 /* Force a read-back to make sure everything is flushed. */
44 dmc_read(DMC_CAV_LUT_DATAH);
45}